IP100A LF
Preliminary Data Sheet
60/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.4.16 RxDMAListPtr
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x10
Default .......................... 0x00000000
Width ............................ 32 bits
RxDMAListPtr is the physical address of the current receive DMA Frame Descriptor in the Receive DMA
List. A value of 0x00000000 for RxDMAListPtr indicates that no more RFDs are available to accept
receive frames. RxDMAListPtr only points to addresses on 8-byte boundaries, so RFDs must be aligned
on 8-byte physical address boundaries. RxDMAListPtr may be written directly by the host system to point
the IP100A LF to the head of a newly created Receive DMA List. RxDMAListPtr is also updated by the
IP100A LF as it processes RFDs in the Receive DMA List. As the IP100A LF finishes processing a RFD,
it loads RxDMAListPtr with the value from the RxDMANextPtr field of the current RFD in order to move
on to the next RFD in the Receive DMA List. If the IP100A LF loads a value of 0x00000000 from the
current RFD, the receive DMA logic enters the idle state, waiting for a non-zero value to be written to
RxDMAListPtr. To avoid access conflicts between the IP100A LF and the host system, the host system
must set the RxDMAHalt bit in the DMACtrl register before writing to RxDMAListPtr.
BIT
BIT NAME
R/W
BIT DESCRIPTION
31..0
RxDMAListPtr
R/W
Receive DMA List Pointer. RxDMAListPtr is the physical address,
on a 8-byte boundary, of the current RFD in the Receive DMA List.
11.4.17 RxDMAPollPeriod
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x16
Default .......................... 0x00
Width ............................ 8 bits
RxDMAPollPeriod determines the rate at which the current RFD’s RxDMAComplete bit of the
RxFrameStatus field in the RFD is polled for a logic 0. Polling is disabled when RxDMAPollPeriod is 0x00.
RxDMAPollPeriod is specified in increments of 320 ns. The maximum value is 127 (or 40.64 us).
BIT
BIT NAME
R/W
BIT DESCRIPTION
6..0
RxDMAPollPeriod
R/W
Receive DMA Poll Period. RxDMAPollPeriod is the number of
320ns intervals between polls of the RxDMAComplete bit in the
RxFrameStatus field of the current RFD.
7
Reserved
N/A
Reserved for future use.
11.4.18 RxDMAStatus
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x0c
Default .......................... 0x00000000
Width ............................ 32 bits
RxDMAStatus shows the status of various operations in the receive DMA logic. Host systems should
read RxDMAStatus only if the RxDMAHalted bit in the DMACtrl register is a logic 1. Otherwise the
IP100A LF may change RFDs between accesses to RxDMAStatus. Many bits of RxDMAStatus are
identical to corresponding bits of the RxFrameStatus field.
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