IP100ALF datasheet(45/97 Pages) ETC2

45 / 97 page

IP100A LF

Preliminary Data Sheet

45/97

March. 30, 2007

IP100A LF-DS-R17

BIT

BIT NAME

R/W

BIT DESCRIPTION

been received.

1 and 0 indicates the

data receiving is in

progress.

LED_DPLXN Logic 0 means the link is

established based on

FULL Duplex Mode,

while logic 1 indicates

HALF Duplex Mode.

Alternating logic 1 and 0

indicates COLLISION

has occurred.

Logic 0 means the link

is established based on

FULL Duplex Mode,

while logic 1 indicates

HALF Duplex Mode.

TxLargeEnable

R/W

Transmit Large Frames Enable. If TxLargeEnable is a logic 1, the

IP100A LF may transmit frames which are larger in size than the

IP100A LF transmit FIFO.

RxLargeEnable

R/W

Receive Large Frames Enable. If RxLargeEnable is a logic 1, the

IP100A LF may receive frames which are larger than the IP100A

LF receive FIFO.

ExpRomDisable

R/W

Expansion ROM Disable. If ExpRomDisable is a logic 1,

accesses to the on-adapter Expansion ROM are disabled and

read to the Expansion ROM return 0x00000000 while writes to

the Expansion ROM are ignored.

PhySpeed10

Physical Device 10Mbps Capable. If PhySpeed10 is a logic 1, the

IP100A LF PHY is capable of operating at 10Mbps.

PhySpeed100

Physical Device 100Mbps Capable. If PhySpeed100 is a logic 1,

the IP100A LF PHY is capable of operating at 100Mbps.

PhyMedia

Physical Device Media Type. If PhyMedia is a logic 0, copper

media is in use. If PhyMedia is a logic 1, fiber media is in use. The

combination of PhyMedia, PhySpeed100, and PhySpeed10

defines the capabilities of the PHY.

PHY

MEDIA

PHY

SPEED100

PHY

SPEED10

PHY CAPABILITY

Undefined

10BASE-T

100BASE-T

100BASE-T or 10BASE-T

Undefined

10BASE-F

100BASE-F

100BASE-F or 10BASE-F

9..8

ForcedConfig[1..0]

R/W

Forced Configuration. ForcedConfig[1..0] is used to enable and

select a Forced Configuration mode for the IP100A LF. Forced

Configuration mode is targeted toward embedded applications

which do not utilize an EEPROM. In Forced Configuration mode,

the IP100A LF is accessed via a PCI bus without first performing

PCI configuration or loading parameters from an EEPROM.

The ForcedConfig[1..0] bits 9 through 8 can also be set on reset

using ED[4:3].

BIT 9

BIT 8

FORCED CONFIGURATION MODE

None

IP100ALF 数据表(PDF) 45 Page - List of Unclassifed Manufacturers

IP100ALF 数据表(HTML) 45 Page - List of Unclassifed Manufacturers

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