IP100A LF
Preliminary Data Sheet
49/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
BIT
BIT NAME
R/W
BIT DESCRIPTION
14
TxDMAInProg
R
Transmit DMA in Progress. If TxDMAInProg is a logic 1, a
transmit DMA operation is in progress. TxDMAInProg is primarily
used by the host system in an under run recovery routine. The
host system waits for TxDMAInProg to be a logic 0 before setting
the TxReset bit of the AsicCtrl register to clear the under run
condition. Before checking TxDMAInProg, issue TxDMAHalt.
15
DMAHaltBusy
R
DMA Halt Busy. DMAHaltBusy indicates that a DMA Halt
operation (TxDMAHalt or RxDMAHalt) is in progress and the host
system should wait for DMAHaltBusy to be cleared before
performing other actions.
16
Reserved
N/A
Reserved for future use.
17
Reserved
N/A
Reserved for future use.
18
Reserved
N/A
Reserved for future use.
19
Reserved
N/A
Reserved for future use.
20
MWIDisable
R/W
PCI MWI Command Disable. If Setting MWIDisable is a logic 1,
the IP100A LF will not use the Memory Write Invalidate (MWI)
PCI command.
21
Reserved
N/A
Reserved for future use.
22
RxDMAOverrun-
Frame
R/W
Receive DMA Overrun Frame. If RxDMAOverrunFrame is a logic 0,
receive DMA will discard receive overrun frames without transferring
them to the host system. WhenRxDMAOverrunFrame is a logic 1,
receive DMA will transfer overrun frames to the host system.
Overrun frames are any frame which is received while the receive
FIFO is full.
29..23
Reserved
N/A
Reserved for future use.
30
TargetAbort
R
Bus Target Abort. TargetAbort is a logic 1 when the IP100A LF
experiences a target abort sequence when operating as a bus
master. TargetAbort indicates a fatal error, and must be cleared
before further transmit DMA or receive DMA operation can
proceed. TargetAbortt is cleared via the GlobalReset, and DMA
bits of the AsicCtrl register.
31
MasterAbort
R
Bus Master Abort. MasterAbort is a logic 1 when the IP100A LF
experiences a master abort sequence when operating as a bus
master. MasterAbort indicates a fatal error, and must be cleared
before further transmit DMA or receive DMA operation can
proceed. MasterAbortt is cleared via the GlobalReset, and DMA
bits of the AsicCtrl register.
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