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STA382BWSTR 数据表(PDF) 122 Page - STMicroelectronics |
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STA382BWSTR 数据表(HTML) 122 Page - STMicroelectronics |
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122 / 172 page  Register description: Sound Terminal compatibility STA382BWS 122/172 Doc ID 022784 Rev 1 7.6.2 Invalid input detect mute enable Setting the IDE bit enables this function, which looks at the input I2S data and automatically mutes if the signals are perceived as invalid. 7.6.3 Binary output mode clock loss detection This bit detects loss of input MCLK in binary mode and will output 50% duty cycle. 7.6.4 LRCK double trigger protection This bit actively prevents double triggering of LRCLK. 7.6.5 Auto EAPD on clock loss When active, this bit issues a device power-down signal (EAPD) on clock loss detection. 7.6.6 IC power-down The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down the power stage, then the master clock to all internal hardware except the I2C block is gated. This places the IC in a very low power consumption state. Table 127. Invalid input detect mute enable Bit R/W RST Name Description 2 R/W 1 IDE Setting of 1 enables the automatic invalid input detect mute Table 128. Binary output mode clock loss detection Bit R/W RST Name Description 3 R/W 1 BCLE Binary output mode clock loss detection enable Table 129. LRCK double trigger protection Bit R/W RST Name Description 4 R/W 1 LDTE LRCLK double trigger protection enable Table 130. Auto EAPD on clock loss Bit R/W RST Name Description 5 R/W 0 ECLE Auto EAPD on clock loss Table 131. IC power-down Bit R/W RST Name Description 7R/W 1 PWDN 0: IC power-down low-power condition 1: IC normal operation Obsolete Product(s) - Obsolete Product(s) |
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