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L9963E 数据表(PDF) 63 Page - STMicroelectronics |
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L9963E 数据表(HTML) 63 Page - STMicroelectronics |
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63 / 184 page  Figure 19. SPI timing diagram All parameters are tested and guaranteed in the following conditions, unless otherwise noted: 9.6 V < VBAT < 64 V; -40 °C < Tambient < 105 °C Table 51. SPI electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit Tcll Minimum time CLK = LOW Application info 75 ns Tclh Minimum time CLK = HIGH Application info 75 ns Tpcld Propagation delay (SCLK to data at SDO active) Cload = 30 pF Valid for GPIO9 50 ns Tlead CLK change L/H after NCS = low Application info 75 ns Tscld SDI input setup time (CLK change H/L after SDI data valid) Application info 15 ns Thcld SDI input hold time (SDI data hold after CLK change H/L) Application info 15 ns Tsclch CLK low before NCS low Application info 75 ns Tlag CLK low before NCS high Application info 100 ns Thclch CLK high after NCS high Application info 100 ns Tonncs NCS min high time Application info 300 ns Tpchdz NCS L/H to SDO @ high impedance Cload = 30 pF Valid for GPIO9 75 ns Tcsdv NCS H/L to SDO active Cload = 30 pF Valid for GPIO9 90 ns FCLK_SPI CLK frequency (50% duty cycle) Application info 0.5 5 MHz TSPI_ERR Tested by SCAN 5 ms RPULLDOWN_SPIEN Pulldown resistance on SPIEN pin 50 150 kΩ 4.10 Internal Non Volatile Memory (NVM) L9963E offers the possibility to store pack ID and other sensitive data in the internal NVM, up to NNVM_SIZE bit. Three operations are available: L9963E Internal Non Volatile Memory (NVM) DS13636 - Rev 12 page 63/184 |
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