L9963E datasheet(24/184 Pages) STMICROELECTRONICS

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Figure 10. Isolated SPI pulse shape and logical meaning

4.2.3.1

ISO communicator receiver and transmitter

An isolated receiver and transmitter are connected to the couple of pins ISOLP/M and ISOHP/M. Depending on

the communication phase, they can be enabled or disabled.

4.2.3.1.1

ISO communicator receiver

The receiver is able to convert a differential input signal into a single ended signal that is provided to the logic.

In order to guarantee a correct communication and guarantee Wake up via Communication Interface the input

common mode must be included into range VCM_ISO_IN.

At power up by default the device is configured for a low frequency communication (FISO_SLOW); higher frequency

FISO_FAST can be configured by acting on the iso_freq_sel bit.

4.2.3.1.2

ISO communicator transmitter

The transmitter is able to force as differential output the single ended signal that is provided by the logic.

Transmitter output impedance can be programmed via out_res_tx_iso (RDIFF_ISO_OUT1…3), as described in

Table 18. It affects differential pulse amplitude. In order to guarantee a correct communication in case of high

frequency configuration the bit length must be at least TBIT_LENGTH_FAST and the duration of high and low level of

a single bit into a period TBIT_LENGTH_FAST must be TBIT_HIGH_LOW_FAST.

In case of low frequency configuration TBIT_LENGTH_SLOW and TBIT_HIGH_LOW_SLOW are valid.

4.2.3.2

Dual access ring

L9963E supports dual access ring topology (refer to Section 6.11.3 Dual access ring for the application

scenario). The device accepts commands from both ports (ISOL/SPI and ISOH ports) and generates answers in

both directions.

This kind of functionality is present by default and cannot be disabled.

In the typical application scenario featuring a number of NDEVICES L9963E, two of them are configured as SPI

devices (referred to as bottom and top Masters), while the remaining is configured as isolated SPI slaves (refer to

Section 4.2.1 Communication interface selection for Master and Slave behavior).

Referring to Figure 51, the Section 4.1.2.2 Addressing procedure follows the standard approach, except for the

top Master, that must be initialized through its own SPI interface.

Once the initialization is complete, MCU is able to communicate with any Slave through any of the 2 Masters SPI

interface. It is also possible to verify the loop integrity, accessing one Master through the opposite one.

In case the access to a Slave is performed exploiting the bottom Master, the corresponding answer must be

retrieved through the bottom Master itself (the same applies for the dual case of the top Master).

L9963E

Serial communication interface

DS13636 - Rev 12

page 24/184

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