L9963E datasheet(40/184 Pages) STMICROELECTRONICS

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4.4

Cell voltage measurement

A level shifter is able to report the cell voltage at the input of the low voltage cell ADC.

All cells are acquired in parallel, with no desynchronization between samples. Immunity to differential noise can

be increased by tuning the acquisition window TCYCLEADC.

The user may program the voltage acquisition window TCYCLEADC among 8 different values:

•

The whole option set is available for both ADC_FILTER_SOC and ADC_FILTER_CYCLE. These

parameters apply respectively to On-Demand Conversions and Cyclic Conversions

•

The first 4 rows are available for ADC_FILTER_SLEEP configuration. This parameter applies to Cyclic

Conversions performed in Cyclic Wakeup

For further information, refer to Section 4.12 Voltage conversion routine.

Table 38. Selection of the ADC filter values

Parameter

Code Window amplitude (typ)

Recommended wait time

TDATA_READY

Minimum sample time

achievable TSAMPLE_MIN

TCYCLEADC_000 000

290 μs

380 μs

760 μs

TCYCLEADC_001 001

1.16 ms

1.34 ms

2.68 ms

TCYCLEADC_010 010

2.32 ms

2.61 ms

5.22 ms

TCYCLEADC_011

011

9.28 ms

10.27 ms

20.54 ms

TCYCLEADC_100 100

18.56 ms

20.48 ms

40.96 ms

TCYCLEADC_101 101

37.12 ms

40.89 ms

81.78 ms

TCYCLEADC_110

110

74.24 ms

81.72 ms

163.44 ms

TCYCLEADC_111

111

148.48 ms

163.4 ms

326.8 ms

Cell measurement results are stored in Vcellx registers and are 16-bit wide. To obtain the result, apply the

following formula:

Cell voltage measurement

VCELL=BINARY_CODE×VCELLRES

(2)

After launching a cell conversion, the MCU should wait at least for the recommended wait time TDATA_READY

before retrieving the cell data. This allows L9963E to perform sample interpolation and calibration.

The data readiness is confirmed by the assertion of:

•

d_rdy_Vcellx bit for VCELLx registers

•

d_rdy_gpiox bit for GPIOx_MEAS registers

•

d_rdy_vtref bit for VTREF register

•

data_ready_vbattdiv for VBATT_DIV register

•

data_ready_vsum for vsum_batt19_0 register

Polling the data ready bit is possible but not recommended, since it causes a higher consumption from the battery

stack due to communication.

Note:

If Coulomb Counting Routine is activated, MCU should add TCYCLEADC_CUR to the TDATA_READY wait time

in order to account for the maximum synchronization delay between voltage and current samples. For further

information refer to Section 4.13.1 Coulomb counting.

Before launching another conversion, MCU should wait at least for the recommended minimum TSAMPLE in order

to avoid conflict with previous conversions. In case this happens, the new request will be discarded.

Hence, given a differential signal with bandwidth BW:

•

The MCU should sample it using at least TSAMPLE = 1 / 2BW, in order to fulfill Nyquist criterion

–

All the TCYCLEADC_XXX values in Table 38, whose TSAMPLE_MIN is lower than TSAMPLE can be

exploited in application;

L9963E

Cell voltage measurement

DS13636 - Rev 12

page 40/184

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