L9963E datasheet(69/184 Pages) STMICROELECTRONICS

69 / 184 page

Note:

When performing PCB open diagnostic, other diagnostics such as Cell UV/OV diagnostic and Balancing open

load diagnostic might also be triggered. They must be then discarded by user SW.

4.11.6

Voltage ADC BIST

Besides Cell open with ADC_CROSS_CHECK = 1, the HardWare Self-Check (HWSC) step of the Voltage

Conversion Routine covers all the additional conversion paths, such as VTREF, GPIOs configured as analog

input and VBAT resistive divider. As a redundant mechanism, it also covers conversion paths involving Cx pins.

If BIST result is not aligned to expectations:

•

Corresponding fault flag is set and latched into register MUX_BIST_FAIL or OPEN_BIST_FAIL or

GPIO_BIST_FAIL

•

Fault is propagated through the FAULT Line

•

Balance is stopped

•

Voltage conversion routine goes into Configuration Override

For further details see Section 4.12 Voltage conversion routine.

4.11.7

Die temperature diagnostic and over temperature

An internal temperature sensor continuously monitors the temperature of the chip: measurement result is

available in the TempChip register and can be evaluated according to the following formula:

Temperature Measurement Formula

Tj=1.3828×BINARYCODE+99.733

(10)

TJ is in °C and the binary code is in 2’s complement format.

The chip prevents over-heating through an over temperature threshold TSD (which includes a hysteresis

TSD_HY). Once the die temperature reaches TSD, a thermal shutdown circuit will force the chip to reduce the

consumption by stopping balancing. A fault is reported to the μC with a dedicated bit OTchip and propagated

through the FAULT Line. When the temperature of the die returns to a normal level, L9963E can resume the

normal operation. Balancing is released after the uC reads OTchip latch.

4.11.8

Balancing open load diagnostic

During Balancing open load diagnostic a pulldown current IPD_CB is applied through the balancing path, including

the discharge resistor. A voltage comparator is able to detect whether the voltage |Sn-Bn,n-1|, in Power balance

OFF condition, falls below the open load threshold VBAL_OPEN. If TOPEN – TNOT_OPEN > TBAL_OL/2 , the open load

fault (BALx_OPEN) is latched.

Note:

TOPEN is the time interval where the comparator output is high (open fault present), while TNOT_OPEN is the time

interval where the comparator output is low (open fault not present).

Balance comparator has a self test mechanism used to check internal integrity. In case BIST fails

(BIST_BAL_COMP_HS_FAIL or BIST_BAL_COMP_LS_FAIL), balancing is stopped.

The equivalent open load resistance in series to the balancing path can be evaluated according to the following

equation:

Equivalent balance open resistance estimation

RBALOPEN=VCELL−VBAL_OPEN

IPD_CB

(11)

L9963E

Safety and diagnostic features

DS13636 - Rev 12

page 69/184

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