L9963E datasheet(75/184 Pages) STMICROELECTRONICS

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4.11.22

Communication integrity

The communication frame is checked and verified to ensure the information is valid.

A Cyclic Redundancy Check (CRC) is used to ensure the serial data read from L9963E is valid and has not been

corrupted even in application environments of high noise. For further information, refer to Section 4.2.4.6 CRC

calculation.

4.11.23

Communication loss detection

In case no valid communication frame is received for t > t_SLEEP (programmable via CommTimeout bit), the

Comm_timeout_flt latch is set and the device moves to Sleep or Silent Balancing state, depending on the

slp_bal_conf bit.

In a vertical interface arrangement, any command addressing a slave unit will pass through the whole chain, thus

serving the communication timeout for all the units. On the contrary, polling the Master unit is not a good strategy

to refresh the communication timeout.

Communication timeout is enabled by default, but can be disabled by programming comm_timeout_dis = ‘1’.

For further information about Master and Slaves, refer to Section 4.2.1 Communication interface selection.

4.11.24

Rolling counter

To improve fault coverage on unintended message repetition, a rolling counter functionality has been

implemented. MCU can send a MOSI frame setting a certain value for the Rolling Counter bit (LSB of the Global

Status Word (GSW)). L9963E will answer setting the same Rolling Counter value in the next communication

iteration (protocol is out of frame). So that this safety mechanism to be effective, MCU should continuously toggle

the rolling counter bit each MOSI frame.

4.11.25

Trimming and calibration data integrity check

This safety mechanism checks:

•

The trimming and calibration data stored in internal EEPROM. This is done everytime the NVM is

downloaded (EEPROM_DWNLD_DONE 0 → 1). In case one of the EEPROM sectors is corrupted, the

following error bit will be set:

–

EEPROM_CRC_ERR_SECT_0 covers the trimming data

–

EEPROM_CRC_ERR_CAL_RAM covers the calibration data used by the Voltage Conversion

Routine

–

EEPROM_CRC_ERR_CAL_FF covers the calibration data used by the Coulomb Counting Routine

•

The data loaded into RAM, everytime it is requested by the Voltage Conversion Routine and Coulomb

Counting Routine. In case of error, the following bit will be set:

–

RAM_CRC_ERR covers the data stored in RAM

–

The RAM correct functionality is guaranteed by BIST

NVM is downloaded upon first power up. Manual connection of battery cells might cause first power up failure due

to slow stack voltage increase. In such a case, NVM first download might fail. Once the device has been correctly

woken up, MCU shall check all the NVM error bit and, in case of data corruption, trimming data re-download can

be triggered by attaining to the following procedure:

Set trimming_retrigger = ‘1’;

Wait for Inter-frame Delay;

Set trimming_retrigger = ‘0’;

Check all NVM error bit to confirm trimming and calibration data integrity;

Wait for at least timeout_VCOM_UP_first before executing any conversion.

4.11.26

FAULT heart beat

The heart beat functionality of the fault line guarantees continuous fault line integrity monitoring. Moreover,

it acts as a windowed watchdog, where every stacked device monitors its upper companion. Refer to

Section 4.3 FAULT line for further information.

L9963E

Safety and diagnostic features

DS13636 - Rev 12

page 75/184

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