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L9963E 数据表(PDF) 138 Page - STMicroelectronics |
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L9963E 数据表(HTML) 138 Page - STMicroelectronics |
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138 / 184 page  Components Value Unit Max. tolerance Rating Comments MREG 3 V VGS_TH max VDS ≥ 80V The STL8N10LF3 (single FET) is recommended for applications requiring optimized thermal performances The STL8DN10LF3 (dual FET) is recommended for applications requiring also a higher safety integrity level. Alternatively, the STD25NF10LA is also supported. For all components, follow MOSFET datasheet in order to optimize Rth value. CREG 4.7 µF 10% 16 V Tank for the VREG regulator. Mount as close as possible to VREG pin. Connect to AGND 6.6 Cell balancing circuits 6.6.1 Cell balancing with internal MOSFETs Figure 37. Cell monitoring with internal balancing C10 S10 B10_9 C9 S9 RLPF RLPF C8 RLPF RDIS RDIS CLPF CLPF L9963E • Force lines used for balancing. Connect them as close as possible to the cell connector. This improves cell voltage sensing while balancing is ongoing, by minimizing the voltage drop on the sense lines while current is being sunk • Sense lines used for cell voltage measurement. Keep away from noisy lines. Recommended PCB layout strategy is to route them over the first layer and shield them using the second layer as GND plane Table 77. Internal balancing components with recommended values Components Value Unit Max. tolerance Rating Comments RDIS 39 Ω 10% 3/4 W Any value is possible, as long as the cell balance current does not exceed the required current limitation (200 mA). Maximum cell balance current in application is IBALmax=VCELLmax RDIS Mounting less than 39 Ω may seriously jeopardize hotplug capability of the internal balancing FETs. Do not use thin film resistors on these lines connected to ECU global pins. They could drift upon System Level ESD strikes. Use thick film or metal foil instead. L9963E Cell balancing circuits DS13636 - Rev 12 page 138/184 |
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