L9963E datasheet(182/184 Pages) STMICROELECTRONICS

182 / 184 page

List of figures

Figure 1.

Typical application.................................................................. 4

Figure 2.

Block diagram .................................................................... 5

Figure 3.

Pin connections (top view) ............................................................ 6

Figure 4.

Device operation in the VBAT supply voltage ranges ......................................... 10

Figure 5.

Sketch of a 2s2p PCB with thermal vias .................................................. 12

Figure 6.

Device functional states ............................................................. 14

Figure 7.

Daisy chain addressing algorithm ...................................................... 16

Figure 8.

Power up Sequence ............................................................... 17

Figure 9.

Isolated SPI interface .............................................................. 23

Figure 10.

Isolated SPI pulse shape and logical meaning ............................................. 24

Figure 11.

Out of frame protocol description ...................................................... 27

Figure 12.

Write and read access .............................................................. 27

Figure 13.

Single read access ................................................................ 28

Figure 14.

Burst access .................................................................... 29

Figure 15.

False failure detection due to sudden heartbeat disable during the duty phase ....................... 39

Figure 16.

Cell monitoring with Internal balancing ................................................... 47

Figure 17.

Cell monitoring with external balancing with the mixed NMOS and PMOS transistors................... 47

Figure 18.

Regular scheme .................................................................. 55

Figure 19.

SPI timing diagram ................................................................ 63

Figure 20.

Equivalent open resistance vs.cell voltage ................................................ 70

Figure 21.

GPIO open resistance vs. temperature .................................................. 73

Figure 22.

Voltage conversion routine ........................................................... 84

Figure 23.

Routine execution modes: on-demand and cyclic executions ................................... 86

Figure 24.

Equivalent FSM behavior of the voltage conversion routine .................................... 88

Figure 25.

Example of routine execution in normal mode.............................................. 90

Figure 26.

Example of configuration override: a failure detected during Cell Terminal diagnostics (yellow background) causes

the following two steps (red background) to be executed ...................................... 93

Figure 27.

Grounds collection node ........................................................... 129

Figure 28.

Layout example of ground connections ................................................. 130

Figure 29.

Example of best practice for splitting cell force and sense lines ................................. 131

Figure 30.

Recommended routing technique in order to reduce additional spikes due to lanes parasitic inductance .... 132

Figure 31.

Layout for ESD protections according to the recommended technique ............................ 132

Figure 32.

Typical application circuit ........................................................... 133

Figure 33.

Typical cell voltage sensing circuit ..................................................... 135

Figure 34.

Fail Safe in case of open on busbar.................................................... 136

Figure 35.

Typical current sensing analog front end ................................................ 136

Figure 36.

VREG regulator circuits ............................................................ 137

Figure 37.

Cell monitoring with internal balancing .................................................. 138

Figure 38.

Cell monitoring with external balancing with the mixed NMOS and PMOS transistors.................. 139

Figure 39.

FAULT link between daisy chained devices .............................................. 141

Figure 40.

Recommended FAULT line design in a centralized BMS ..................................... 144

Figure 41.

Transformer based ISO lines circuit .................................................... 145

Figure 42.

Capacitive based ISO lines circuit ..................................................... 146

Figure 43.

Example of NTC single ended measurement ............................................. 147

Figure 44.

VNTC vs. temperature example (single ended measurement).................................. 148

Figure 45.

Example of NTC differential measurement ............................................... 149

Figure 46.

VNTC vs. temperature example (differential measurement) ................................... 150

Figure 47.

How to handle unmounted cells ...................................................... 152

Figure 48.

How to connect cell modules and busbar ................................................ 154

Figure 49.

Distributed BMS ................................................................. 155

Figure 50.

Centralized BMS................................................................. 156

Figure 51.

Dual access ring ................................................................. 157

L9963E

List of figures

DS13636 - Rev 12

page 182/184

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