PAC1932SLASH3SLASH4 datasheet(20/62 Pages) MICROCHIP

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PAC1932/3/4

DS20005850C-page 20

 2017-2018 Microchip Technology Inc.

Note that the REFRESH_V command may also be

used to activate changes to the Control register, just

like the REFRESH command, except with the

REFRESH_V command changes to the Control

accumulators

accumulator

count.

See

REFRESH_V Command (Address

1Fh).

4.1.5

SLEEP STATE

The SLEEP state is a lower power state than the

Active state. While in this state, the device will draw a

supply current of ISLEEP from the VDD pin. The device

automatically goes to this state between conversion

cycles when sampling rates lower than 1,024

samples/second are selected, or if fewer than four

channels are active. All digital states and data are

retained in the SLEEP state. The device can also be

put in the Sleep state by setting the SLEEP bit

followed by a REFRESH or REFRESH_V command,

and sampling will resume when the SLEEP bit is

cleared followed by a REFRESH of REFRESH_V

command. The device does not go into SLEEP state

based on any other condition such as static conditions

on the SMBus pins. If SMBus Timeout is enabled, it is

supported in SLEEP mode or ACTIVE mode.

4.1.6

POWER-DOWN STATE

The Power-Down state is entered by pulling the

PWRDN pin low. In this state, all circuits on the chip

including the SMBus pins are inactive, and the device

is in a state of minimum power dissipation.

In the Power-Down state, no data is retained in the

chip (neither register configuration nor measurement

data). When the PWRDN pin is pulled high,

integration, measurement and accumulation will begin

using the default register settings, as described in

Section 4.1.1 “Initial Operation and Active State”

The first measurement data may be requested by a

REFRESH or REFRESH_V command 20 ms after the

PWRDN pin is pulled high.

4.1.7

PROGRAMMING THE SAMPLE

RATE AND THE SLOW PIN

The default sampling rate after power-up is 1024

samples/second. Sampling rates of 256, 64 or 8

samples/second

may

programmed

the

CTRL Register (Address 01h). Any time

a new sample rate is programmed, it does not take

effect

until

REFRESH,

REFRESH_G,

REFRESH_V command is received. When any of

these REFRESH commands are received, any

round-robin sampling cycle in progress will complete

before the new sampling rate takes effect. For

example, if the user is sampling at 8 SPS and program

a new sample rate, it may take up to 125 mS for the

new sample rate to take effect and for all the sample

rate related registers (like CTRL_ACT) to show their

updated values.

If one of these lower sample rates is used, power

dissipation is reduced. The round-robin sampling and

conversion cycle is exactly the same, but the device

goes into the sleep state between conversion cycles.

See Section 2.0 “Typical Operating Curves”.

If the SLOW pin is pulled high, the device will sample

at eight samples/second. No matter what the

programmed sample rate, this new SLOW sample rate

will take effect on the next conversion cycle (if a

round-robin conversion cycle is in process when the

SLOW pin goes high, that conversion cycle will

complete before the SLOW sample rate takes effect.)

If the device is programmed for Single Shot mode, and

the SLOW pin is asserted, the first sampling will begin

within 125 ms after the SLOW pin is asserted.

If the device is in the Sleep state, asserting the SLOW

pin will not cause sampling to start.

Whenever the SLOW pin changes state, a limited

REFRESH or REFRESH_V command may be

executed by the chip hardware (default is REFRESH).

Like any other REFRESH command, this resets the

accumulators and accumulator count for a REFRESH

command, and updates the readable registers for

either REFRESH or REFRESH_V. These are limited

REFRESH commands because no programmed

changes to the Control or Status registers take effect

(Control and Status registers means registers 01h,

1Ch, 1Dh, and 20h-26h). The readable registers are

stable with the new values within 1 ms of the SLOW

pin transition.

The Slow register enables selection of REFRESH or

REFRESH_V on the SLOW pin transitions, which

allows this function to be disabled for either edge, and

also tracks both the state of the SLOW pin and

transitions on the SLOW pin. See Register 6-14,

SLOW (Address 20h).

This is the default functionality of the SLOW pin, but it

may be reconfigured to function as an ALERT pin (see

paragraph Section 4.4 “Alert Functionality”). If the

SLOW pin is configured to serve as an ALERT pin, the

slower sampling rate of eight samples/second is only

available by programming the Control register 01h.

4.2

Conversion Cycles

A conversion cycle for the device consists of

analog-to-digital conversion being complete for all

channels (including the real-time calibration that is part

of each conversion cycle). Immediately following the

data conversion, the power results are calculated for

that channel and the power value is added to the

accumulator. Averaged values for VSENSE and VBUS

are also updated internally as part of each conversion

cycle.

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