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PAC1932/3/4 数据表(PDF) 49 Page - Microchip Technology |
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PAC1932/3/4 数据表(HTML) 49 Page - Microchip Technology |
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49 / 62 page ![]() 2017-2018 Microchip Technology Inc. DS20005850C-page 49 PAC1932/3/4 bit 1 OVF ALERT : shows the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G) for the OVF_ALERT bit. 0 = No ALERT if accumulator or accumulator counter overflow has occurred 1 = ALERT pin triggered if accumulator or accumulator counter has overflowed bit 0 OVF : shows the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G) for the OVF bit. 0 = No accumulator or accumulator counter overflow has occurred 1 = Accumulator or accumulator counter has overflowed REGISTER 6-19: CHANNEL DIS_LAT (ADDRESS 25H) R-0 R-0 R-0 R-0 U U U U CH1_OFF CH2_OFF CH3_OFF CH4_OFF — — — — bit 7 bit 0 Legend: R = Readable bit W = Writeable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown This register contains an image of the Register 6-16 Channel DIS_ACT (Address 22h).The bits in this register reflect the value of these settings that was active before the most recent REFRESH command (including REFRESH_V and/or REFRESH_G). The values in register 1Ch may have been programmed but not activated by one of the REFRESH commands, and the values in 22h are currently active. This register allows software to determine the actual active setting that was active prior to the most recent REFRESH command and therefore corresponds to the dataset that is held in the readable registers. This register is valid when the Results registers are valid, 1 ms after a REFRESH/_V/_G command. bit 7-4 CHn_OFF<7:4> : the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G). bit 7 0 = CH1 ON. Channel 1 active during conversion cycle 1 = CH1 OFF. Channel 1 inactive during conversion cycle bit 6 0 = CH1 ON. Channel 2 active during conversion cycle 1 = CH1 OFF. Channel 2 inactive during conversion cycle bit 5 0 = CH1 ON. Channel 3 active during conversion cycle 1 = CH1 OFF. Channel 3 inactive during conversion cycle bit 4 0 = CH1 ON. Channel 4 active during conversion cycle 1 = CH1 OFF. Channel 4 inactive during conversion cycle bit 3-0 Not used, always read ‘0’ REGISTER 6-18: CTRL_LAT REGISTER (ADDRESS 24H) |
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