PAC1932SLASH3SLASH4 datasheet(32/62 Pages) MICROCHIP

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PAC1932/3/4

DS20005850C-page 32

 2017-2018 Microchip Technology Inc.

6.0

REGISTERS IN HEXADECIMAL

ORDER

The registers shown in Table 6-1 are accessible

through the SMBus. In the individual register tables that

follow, an entry of ‘—’ indicates that the bit is not used

and will always read ‘0’.

Data represented by the data registers are ensured to

be synchronized and stable 1 ms after any of the

REFRESH commands are sent. Immediately after the

REFRESH commands are sent, the data bytes will be

changing dynamically until 1 ms has elapsed. When

new data is written to a Control register, and the master

reads it back, this new data will be read back even if no

REFRESH command has been sent to cause the new

data to take effect.

Note:

The letter N or n is used to represent

1,2,3,4 in the register and bit names

below, in sections that describe registers

that are grouped for all four channels.

Note:

For PAC1932, channels 3 and 4 do not

contain validate data and will read FF. The

auto-incrementing pointer will skip these

channels by default (see Section 5.5

“Auto-Incrementing

Pointer”

The

same applies to channel 4 for the

PAC1933.

TABLE 6-1:

Number

Description

Type

Bytes

POR

Value

REFRESH Command (Address 00h)

Send Byte for REFRESH command

SEND

00h

CTRL Register (Address 01h)

Configuration controls and status

R/W

00h

ACC_COUNT Register (Address 02h)

Accumulator count for all channels

Block

Read

000000h

VPOWERN Accumulator Registers:

VPOWER1_ACC(03h), VPOWER2_ACC

(04h), VPOWER3_ACC (05h),

VPOWER4_ACC (06h)

Accumulator output for channel 1

Block

Read

Note 1

Accumulator output for channel 2

Block

Read

Note 1

Accumulator output for channel 3

Block

Read

Note 1

Accumulator output for channel 4

Block

Read

Note 1

Note 1:

The VPOWERN Accumulator Registers, 03h-06h, have a POR value that is all zeros: 6 bytes

 000000000000h

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