PAC1932SLASH3SLASH4 datasheet(23/62 Pages) MICROCHIP

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DS20005850C-page 23

PAC1932/3/4

4.8

ADC Measurements, Offset, and

8x Averaging

The PAC1932/3/4 is primarily desired for energy

measurements where many power readings are

accumulated. This is inherently an averaging process.

Individual voltage and current measurements can also

benefit from averaging to reduce noise and offset.

Averaged values are internally calculated for VBUS and

VSENSE, with a rolling average of the most recent eight

values present in the VBUSn_AVG (Register 6-7) and

VSENSEn_AVG (Register 6-6) registers. The average

is updated internally after every conversion cycle. The

readable registers are updated with REFRESH,

REFRESH_V, or REFRESH_G commands like all the

other readable results registers. These averaged

results may be used for the most accurate, lowest

noise and lowest offset measurements.

The ADC channels use a special offset canceling

technique. If the user observes the unaveraged results

for near-zero values of VBUS and VSENSE, they may

observe a cyclical pattern of offset variation. The user

may think this is noise, but in fact it is due to internal

circuitry switching through different permutations of

offset cancellation circuitry. This small variation in

unaveraged offset is canceled in the 8x averaged

result. It is also canceled in the Power Accumulator

results. The overall effect is offset that is consistently

very close to zero LSB over supply and temperature

variations.

The offset canceling technique is illustrated in

Figure 4-4

. It is very difficult to accurately observe, as

it is a challenge to read the data from every conversion

cycle. The effect of capturing data points at a rate that

does not correspond exactly to the internal sampling

rate of the PAC1932/3/4 can make these permutations

appear less periodic and deterministic than they are

inside the chip. The data conversion uses one of the

permute positions 1-4 for each input on each

conversion, cycling through all four permutations in four

conversions. When averaged the Permute Enabled

result shown below is realized, evenly distributed

around zero.

FIGURE 4-4:

Illustration of the Four

Permute Combinations that the ADC Cycles

through and the Resulting Low Average Offset.

Each Bin Represents One Code.

Results from both the VBUS and VSENSE ADCs are 17b

two's complement (signed) internally. There is an addi-

tional bit of resolution that is not accessible from the

results register. The NEG_PWR (Address 1Dh) register

determines whether the conversion results are reported

in the readable registers as unipolar or bipolar numbers.

Using bipolar numbers can give more accurate results

for very small numbers that may actually be negative for

somereadings,inadditiontomeasuringbidirectionalcur-

rents (charging/discharging) and voltages that can dip

below ground.

Averaged values are also calculated for VBUS and

VSENSE. A rolling average of the most recent eight

values is present in the VBUSn_AVG (Register 6-7)

and VSENSEn_AVG (Register 6-6) registers. These

registers require eight conversion cycles after POR

before they represent an accurate value, they are

updated after every conversion cycle. The readable

registers are updated with REFRESH, REFRESH_V

or REFRESH_G commands like all the other readable

results registers.

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