PAC1932SLASH3SLASH4 datasheet(45/62 Pages) MICROCHIP

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DS20005850C-page 45

PAC1932/3/4

SLOW (ADDRESS 20H)

R-0

RW-1

RW-0

RW-1

RW-0

RW-1

SLOW

SLOW-LH

SLOW_HL

R_RISE

R_V_RISE

R_FALL

R_V_FALL

POR

bit 7

bit 0

Legend:

R = Readable bit

W = Writeable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = bit is set

‘0’ = Bit is cleared

x = Bit is unknown

This register tracks the state of the SLOW pin, tracks transitions on the SLOW pin, and controls the type of limited

REFRESH command (if any) that occurs on a SLOW pin transitions. This allows software to monitor the state of the

SLOW pin and its transitions over I2C even though the SLOW pin is asynchronous to the I2C pins and may have a

different controller.

Note that if a REFRESH and REFRESH_V are both enabled for a certain SLOW pin transition, REFRESH will be

executed (REFRESH wins over REFRESH_V).

On a transition of the SLOW pin, a limited REFRESH function is executed. These limited REFRESH and REFRESH_V

functions update all of the readable results registers. For the limited REFRESH function only, it also reset the

accumulators and accumulator count. These are called limited REFRESH and limited REFRESH_V functions because

there is no activation of any pending changes to the Control registers.

If the SLOW pin is configured to act as an ALERT pin, all of these bits are always 0. The bits are not cleared when

read, see the details on each bit for clearing information.

SLOW Control and Status Bits

bit 7 = 0

bit 7 = 1

The SLOW pin is pulled low externally

The SLOW pin is pulled high externally

bit 6 = 0

bit 6 = 1

The SLOW pin has not transitioned low to high since the last REFRESH command

The SLOW pin has transitioned low to high since the last REFRESH command

The bit is reset to 0 by a REFRESH or REFRESH_G command

bit 5 = 0

bit 5 = 1

The SLOW pin has not transitioned high to low since the last REFRESH command

The SLOW pin has transitioned high to low since the last REFRESH command

The bit is reset to 0 by a REFRESH or REFRESH_G command

bit 4 = 0

bit 4 = 1

Disables a limited REFRESH function to take place on the rising edge of the SLOW pin

Enables a limited REFRESH function to take place on the rising edge of the SLOW pin

The bit is not reset automatically, it must be written to be changed.

bit 3 = 0

bit 3 = 1

Disables a limited REFRESH_V function to take place on the rising edge of the SLOW pin

Enables a limited REFRESH_V function to take place on the rising edge of the SLOW pin

The bit is not reset automatically, it must be written to be changed

bit 2 = 0

bit 2 = 1

Disables a limited REFRESH function to take place on the falling edge of the SLOW pin

Enables a limited REFRESH function to take place on the falling edge of the SLOW pin

The bit is not reset automatically, it must be written to be changed

bit 1 = 0

bit 1 = 1

Disables a limited REFRESH_V function to take place on the falling edge of the SLOW pin

Enables a limited REFRESH_V function to take place on the falling edge of the SLOW pin

The bit is not reset automatically, it must be written to be changed

POR Status Bit

The POR bit is a POR flag, for the purpose of enabling the system designer can clear it after POR, and then monitor

it to detect if the device was powered cycled or somehow reset since the POR. If the reset is detected in this manner,

any non-default programming can be reprogrammed.

bit 0 = 0

bit 0 = 1

This bit has been cleared over I2C since the last POR occurred

This bit has the POR default value of 1, and has not been cleared since the last reset occurred

This bit is only reset by POR

PAC1932/3/4 数据表(PDF) 45 Page - Microchip Technology

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PAC1932/3/4 数据表(PDF) 45 Page - Microchip Technology

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