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PAC1932/3/4 数据表(PDF) 7 Page - Microchip Technology |
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PAC1932/3/4 数据表(HTML) 7 Page - Microchip Technology |
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7 / 62 page  2017-2018 Microchip Technology Inc. DS20005850C-page 7 PAC1932/3/4 FIGURE 1-1: SMBus Timing. TABLE 1-2: SMBUS MODULE SPECIFICATIONS Electrical Characteristics : Unless otherwise specified, maximum values are at TA = -40°C to +85°C, VDD = 2.7V to 5.5V, VBUS = 0V to 32V; Typical values are at TA = +25°C, VDD = 3.3V, VBUS = 32V, VSENSE = (SENSE+ – SENSE-) = 0V, VDD I/O = 1.62V to 5.5V Characteristic Sym. Min. Typ. Max. Units Conditions SMBus Interface Input Capacitance CIN — 4 10 pF Not tested in production SMBus Timing Clock Frequency fSMB .010 — 1 MHz No minimum if Time-Out is not enabled. Spike Suppression tSP 0 — 50 ns Bus Free Time Stop to Start tBUF 0.5 — — µs Per SMBus 3.0 Hold Time after Repeated Start Condition tHD:STA 0.26 — — µs Per SMBus 3.0 Repeated Start Condition Setup Time tSU:STA 0.26 — — µs Per SMBus 3.0 Setup Time: Stop tSU:STO 0.26 — — µs Per SMBus 3.0 Setup Time: Start tSU:STA 0.26 — — µs Data Hold Time tHD:DAT 0— — µs Data Setup Time tSU:DAT 50 — — ns Per SMBus 3.0 (Note) Clock Low Period tLOW 0.5 — — µs Per SMBus 3.0 Clock High Period tHIGH 0.26 — 50 µs Clock/Data Fall Time tFALL — — 120 ns Not tested in production Clock/Data Rise Time tRISE — — 120 ns Not tested in production Capacitive Load CLOAD — — 550 pF Per bus line, CLOAD not tested in production SLOW Pin Pulse Width SLOWpw — 100 — µs Pulses narrower than 100 µS may not be detected Note: A device must internally provide a hold time of at least 300 ns for the SM_DATA signal (with respect to the VIH(min) of the SM_CLK signal) to bridge the undefined region of the falling edge of SM_CLK. SMDATA SMCLK TLOW TRISE THIGH TFALL TBUF THD:STA P S S - Start Condition P - Stop Condition THD:DAT TSU:DA T TSU:STA THD:STA P TSU:STO S |
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