EV5424-R-00A datasheet(24/44 Pages) MPS

24 / 44 page

MP5424

– 5V POWER MANAGEMENT IC WITH I2C AND MTP

MP5424 Rev. 1.0

MonolithicPower.com

12/6/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

I2C INTERFACE

I2C Serial Interface Description

The I2C is a two-wire, bidirectional serial

interface consisting of a data line (SDA) and a

clock line (SCL). These lines are pulled up

externally to a bus voltage (VBUS) when idle. A

master device is connected to the line. The

master generates the SCL signal and device

address, and arranges the communication

sequence.

The MP5424 interface is an I2C slave that can

support fast mode (400kHz) and high-speed

mode (3.4Mhz). The I2C interface adds flexibility

to the power supply solution. Among other

parameters, VOUT and the transition slew rate can

be controlled via the I2C interface. If the master

sends the address as an 8-bit value, then the 7-

bit address should be followed by a 0 to indicate

a read (R) operation or 1 to indicate a write (W)

operation.

Start and Stop Conditions

The start (S) and stop (P) conditions are signaled

by the master device, and signify the beginning

and the end of an I2C transfer. The start condition

is defined as the SDA signal transitioning from

high to low while SCL is high. The stop condition

is defined as the SDA signal transitioning from

low to high while SCL is high (see Figure 13).

SDA

SCL

Start Condition

Stop Condition

Figure 13: Start (S) and Stop (P) Conditions

The master then generates the SCL clocks, and

transmits the device address and the read/write

direction bit (R/W) on the SDA line.

Transfer Data

Data is transferred in 8-bit bytes via the SDA line.

Each byte of data should be followed by an

acknowledge (ACK) bit.

I2C Update Sequence

The MP5424 requires a start condition, a valid

I2C address, a register address byte, and a data

byte for a single data update. After receiving

each byte, the MP5424 acknowledges the byte

by pulling the SDA line low during the high period

of a single clock pulse. A valid I2C address

selects the MP5424. The MP5424 performs an

update on the falling edge of the LSB byte.

Figure 14, Figure 15, and Figure 16 show

examples of I2C write and read sequences.

Slave Address

Write Data

8 bits

Master to Slave

Slave to Master

A = Acknowledge (SDA = Low)

S = Start Condition

P = Stop Condition

NA = Not Acknowledge (SDA = High)

Wr (Write) = 0

Rd (Read) = 1

Figure 14: Write Single Register

S Slave Address

A Register Address K

Write Data K

A Write Data K+1 A

Write Data K+N

Multi-byte write executed from current register

location (the read-only register will be skipped)

8 bits

Master to Slave

Slave to Master

A = Acknowledge (SDA = Low)

S = Start Condition

P = Stop Condition

NA = Not Acknowledge (SDA = High)

Wr (Write) = 0

Rd (Read) = 1

Figure 15: Write Multi-Register

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