EV5424-R-00A datasheet(27/44 Pages) MPS

27 / 44 page

MP5424

– 5V POWER MANAGEMENT IC WITH I2C AND MTP

MP5424 Rev. 1.0

MonolithicPower.com

12/6/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

MTP E-Fuse Description

Name

Bits

Default

Description

DVS SLEW

RATE

D[7:6]

Voltage scaling slew rate for the buck 1, buck 2, buck 3, and buck 4 converters. The

soft-start slew rate is set by the SOFTSTART bits.

00: Reserved

01: Reserved

10: 8mV/µs

11: 4mV/µs

FREQUENCY

D[5:4]

Switching frequency (fSW) setting bit.

00: 1.1MHz

01: 1.65MHz

10: 2.2MHz

11: 2.75MHz

PWRON_DEBO

UNCE_TIMER

D[2:1]

Sets the PWRON pin’s debounce timer. It is valid only if PWRON_MODE is set to 1.

See the PWRON_MODE = 1 (Edge Trigger) section on page 21 for more information.

The debounce time is not related to default fSW.

00: 0.5ms

01: 10ms

10: 40ms

11: 160ms

RSTO_MODE

D[7:6]

Sets the RSTO behavior.

00: Does not monitor any power rails. If the PMIC enters the shutdown sequence or

VIN1 drops below its under-voltage lockout (UVLO) threshold, then RSTO goes low.

RSTO goes high once the RSTO delay (tRSTO) is complete

01: Monitors

buck ’s power good (PG). If buck ’s PG (PG4) is good after tRSTO,

RSTO goes high . If buck 4 is turned off by the I2C, then PG4 is high. If PG4 goes low,

then there is no tRSTO

10: Monitors VIN1 (see the RSTO_PFI_THLD register). RSTO goes high if VIN1 > VIN1

UVLO threshold. RSTO goes low if VIN1 < VIN1 UVLO threshold. RSTO goes high after

tRSTO. RSTO goes low with no delay. If VIN1 > VIN1 UVLO threshold and PWRON is

active, then RSTO monitors VIN1 while the PMIC is on

11: Monitors all enabled buck and LDO power rails. If the enabled buck

s’ PG and

LDO

s’ PG are good, then RSTO goes high after tRSTO. If any PG goes low, RSTO

goes low without a delay.

RSTO_DELAY

D[5:4]

Sets tRSTO before RSTO goes high. tRSTO is not related to the default fSW.

00: 100ms

01: 50ms

10: 10ms

11: 1ms

RSTO_PFI_

THLD

D[3:2]

Sets the VIN1 UVLO rising threshold when RSTO_MODE is set to 10.

00: 2.7V

01: 2.9V

10: 4V

11: 4.4V

TIME_SLOT

D[3:2]

Sets the start-up/shutdown sequence time slot intervals. The start-up/shutdown

sequences share the same time slot value. The time slot value is not related to the

default fSW.

00: 0.5ms

01: 2ms

10: 8ms

11: 16ms

EV5424-R-00A 数据表(PDF) 27 Page - Monolithic Power Systems

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