EV5424-R-00A datasheet(31/44 Pages) MPS

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MP5424

– 5V POWER MANAGEMENT IC WITH I2C AND MTP

MP5424 Rev. 1.0

MonolithicPower.com

12/6/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

Name

Bits

Default

Description

EN_OFF_

DELAY

D[4]

Enables the shutdown delay. This bit is only active if EN_OFF_MODE = 0.

0: Shutdown delay disabled. The shutdown sequence begins at the largest time slot

of the enabled channel

1: Enable shutdown delay. The shutdown sequence begins at the 60th time interval,

the power rail turns off once the time interval decreases to the

power rail’s time

interval. The time interval of each power rail is determined by TIME_SLOT,

PWR_OFF_TIME_SLOT_MODE, and the time slot number

EN_OFF_

MODE

D[3]

Sets the shutdown sequence behavior controlled by the PWRON pin. There is always

a shutdown sequence while controlled by EN1.

0: Shutdown sequence

1: No shutdown sequence. All power rails turn off at the same time

DISCHGEN_

LDSW

D[5]

Enable bit for the load switch output discharge function.

0: Discharge function disabled

1: Discharge function enabled

I2C_SLAVE_

ADDRESS

D[4:0]

01001

Sets the A5 to A1 bit of the slave I2C address. See the I2C Bus Slave Address section

on page 34 for more details.

ILIM_LDO4,

ILIM_LDO5

D[6]

Selects the LDO 4 and LDO 5 current limit (ILIMIT).

0: Lower ILIMIT supports 300mA IOUT

1: Higher ILIMIT supports 550mA IOUT

PARALLEL_1

D[7]

Sets whether buck 1 and buck 3 operate in parallel. Use FB1 as the feedback pin.

After the buck converters enter

parallel mode, buck 3’s I2C/MTP register is invalid.

Parallel mode takes effect during a start-up through VIN. After start-up, the PMIC does

not respond to changes on this bit. ILIMIT

is doubled based on buck 1’s register setting.

0: Buck 1 and buck 3 do not operate in parallel

1: Buck 1 and buck 3 operate in parallel

PARALLEL_2

D[6]

Sets whether buck 2 and buck 4 operate in parallel mode. Use FB2 as the feedback

pin. After

the buck converters enter parallel mode

, buck ’s I2C/MTP register is

invalid. Parallel mode takes effect during a start-up through VIN. After start-up, the

PMIC does not respond to changes on this bit. ILIMIT

is doubled based on buck 2’s

0: Buck 2 and buck 4 do not operate in parallel

1: Buck 2 and buck 4 operate in parallel

PWRON_

MODE

D[5]

This bit defines the PWRON pin’s behavior (level trigger or falling-edge trigger).

0: Level trigger. This functions as an EN pin. If

the PWRON pin’s VIN exceeds the

rising threshold, then the PMIC begins the start-up sequence

1: Falling-edge trigger. If the PWRON pin detects a high to low transition and the PMIC

is off, then the PMIC begins the start-up sequence after a delay. If the PMIC is on,

then the PMIC begins the shutdown sequence after a delay. The delay time is set by

PWRON_DEBOUNCE_TIMER

EN_EN1_PIN

D[4]

Enable bit of EN1 function. EN1_POWER_RAILS_CONTROL defines which power

rails are controlled by the EN1 pin. EN1_INV defines EN1 active low or active high.

EN_SELECT defines LSWO or LDO 2 as EN1.

0: EN1 function disabled

1: EN1 function enabled

EN1_INV

D[7]

Sets EN1 to active low or active high.

0: A low-level input to EN1 turns on the corresponding power rails

1: A high-level input to EN1 turns on the corresponding power rails

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