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EV5424-R-00A 数据表(PDF) 30 Page - Monolithic Power Systems |
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EV5424-R-00A 数据表(HTML) 30 Page - Monolithic Power Systems |
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30 / 44 page ![]() MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MP5424 Rev. 1.0 MonolithicPower.com 30 12/6/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Name Bits Default Description POWER_OFF_ SLOT_NO_B1, POWER_OFF_ SLOT_NO_B2, POWER_OFF_ SLOT_NO_B3, POWER_OFF_ SLOT_NO_B4, POWER_OFF_ SLOT_NO_ LDO2, POWER_OFF_ SLOT_NO_ LDSW, POWER_OFF_ SLOT_NO_ LDO4, POWER_OFF_ SLOT_NO_ LDO5 D[7:4] 0011, 0010, 0011, 0001, 0000, 0100 1010 1011 This bit sets each power rail’s time slot number during the shutdown sequence. See the TIME_SLOT register on page 28 and the PWR_OFF_TIME_SLOT_MODE register on page 29 for more details. The delay times between neighboring slots are not related to default fSW. 0000: Time slot 0 0001: Time slot 1 0010: Time slot 2 0011: Time slot 3 0100: Time slot 4 0101: Time slot 5 0110: Time slot 6 0111: Time slot 7 1000: Time slot 8 1001: Time slot 9 1010: Time slot 10 1011: Time slot 11 1100: Time slot 12 1101: Time slot 13 1110: Time slot 14 1111: Time slot 15 POWER_ON_ SLOT_NO_B1, POWER_ON_ SLOT_NO_B2, POWER_ON_ SLOT_NO_B3, POWER_ON_ SLOT_NO_B4, POWER_ON_ SLOT_NO_ LDO2, POWER_ON_ SLOT_NO_ LDSW, POWER_ON_ SLOT_NO_ LDO4, POWER_ON_ SLOT_NO_ LDO5 D[3:0] 0011, 0010, 0011, 0001, 0000, 0100101 0 1011 This bit sets each power rail’s time slot number during the start-up sequence (see the TIME_SLOT register on page 28 and the PWR_ON_TIME_SLOT_MODE register on page 29 for more details). The delay times between neighboring slots are not related to the default fSW. 0000: Time slot 0 0001: Time slot 1 0010: Time slot 2 0011: Time slot 3 0100: Time slot 4 0101: Time slot 5 0110: Time slot 6 0111: Time slot 7 1000: Time slot 8 1001: Time slot 9 1010: Time slot 10 1011: Time slot 11 1100: Time slot 12 1101: Time slot 13 1110: Time slot 14 1111: Time slot 15 DISCHGEN_ LDO2, DISCHGEN_ LDO4, DISCHGEN_ LDO5 D[5] 1 Enable bit for the LDO2, LDO4 and LDO5 output discharge function. 0: Discharge function disabled 1: Discharge function enabled BUCK1_VID, BUCK2_VID, BUCK3_VID D[2:0] 000 Sets the buck 1, buck 2, and buck 3 VOUT range and resolution. 0: VOUT is 400mV to 3.5875V with 12.5mV per step 1: VOUT range is 400mV to 2.2V with 7.4mV per step EN1_SELECT D[5] 0 Selects LSWO or LDO 2 as the EN1 pin. If the EN1 function is enabled, then the corresponding load switch or LDO 2 channel and its discharge function should be turned off. 0: Selects LSWO as EN1 pin 1: Selects LDO2 as EN1 pin |
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