MP5424

– 5V POWER MANAGEMENT IC WITH I2C AND MTP

MP5424 Rev. 1.0

MonolithicPower.com

26

12/6/2021

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© 2021 MPS. All Rights Reserved.

REGISTER DESCRIPTION

MTP E-Fuse Configuration Table

Offset

Name

D7

D6

D5

D4

D3

D2

D1

D0

00

CTL0

DVS SLEW RATE

FREQUENCY

N/A

PWRON_DEBOUNCE_TIMER

N/A

01

CTL1

RSTO_MODE

RSTO_DELAY

RSTO_PFI_THLD

N/A

02

CTL2

N/A

TIME_SLOT

PWR_ON_

TIME_SLOT_

MODE

PWR_OFF_

TIME_SLOT_

MODE

03

Buck 1

BUCK1_VREF: 0.4V to 3.5875V/12.5mV step or 0.4V to 2.2V/7.4mV step

04

N/A

OVPEN1

DISCHGEN1

MODE

BUCK1

N/A

05

ILIM1

PHASE_DELAY1

SOFTSTART1

N/A

06

POWER_OFF_SLOT_NO_B1

POWER_ON_SLOT_NO_B1

07

Buck 2

BUCK2_VREF: 0.4V to 3.5875V/12.5mV step or 0.4V to 2.2V/7.4mV step

08

N/A

OVPEN2

DISCHGEN2

MODE

BUCK2

N/A

09

ILIM2

PHASE_DELAY2

SOFTSTART2

N/A

0A

POWER_OFF_SLOT_NO_B2

POWER_ON_SLOT_NO_B2

0B

Buck 3

BUCK3_VREF: 0.65V to 3.5875V/12.5mV step or 0.4V to 2.2V/7.4mV step

0C

N/A

OVPEN3

DISCHGEN3

MODE

BUCK3

N/A

0D

ILIM3

PHASE_DELAY3

SOFTSTART3

N/A

0E

POWER_OFF_SLOT_NO_B3

POWER_ON_SLOT_NO_B3

0F

Buck 4

BUCK4_VREF: 0.4V to 3.5875V/12.5mV step

10

N/A

OVPEN4

DISCHGEN4

MODE

BUCK4

N/A

11

ILIM4

PHASE_DELAY4

SOFTSTART4

N/A

12

POWER_OFF_SLOT_NO_B4

POWER_ON_SLOT_NO_B4

13

CTL3

N/A

EN1_

SELECT

EN_OFF_

DELAY

EN_OFF_

MODE

BUCK3_VID

BUCK2_VID

BUCK1_VID

14

LDO 2

LDO2_VREF: 0.65V to 3.5875V/12.5mV step

15

N/A

N/A

DISCHGEN_

LDO2

I2C_SLAVE_ADDRESS

16

POWER_OFF_SLOT_NO_LDO2

POWER_ON_SLOT_NO_LDO2

17

LOAD_

SW

N/A

18

N/A

N/A

DISCHGEN_

LDSW

N/A

N/A

19

POWER_OFF_SLOT_NO_LDSW

POWER_ON_SLOT_NO_LDSW

1A

LDO 4

LDO4_VREF: 0.65V to 3.5875V/12.5mV step

1B

N/A

ILIM_

LDO4

DISCHGEN_

LDO4

N/A

N/A

1C

POWER_OFF_SLOT_NO_LDO4

POWER_ON_SLOT_NO_LDO4

1D

LDO 5

LDO5_VREF: 0.65V to 3.5875V/12.5mV step

1E

N/A

ILIM_

LDO5

DISCHGEN_

LDO5

N/A

N/A

1F

POWER_OFF_SLOT_NO_LDO5

POWER_ON_SLOT_NO_LDO5

20

Mode

PARALL

EL_1

PARALL

EL_2

PWRON

_MODE

EN_EN1_

PIN

N/A

N/A

21

EN1

EN1_INV

EN1_POWER_RAILS_CONTROL

22

EN

EN_

BUCK1

EN_

BUCK2

EN_BUCK3

EN_BUCK4

EN_LDO2

EN_LDSW

EN_LDO4

EN_LDO5

23

ID1

MTP configure code ("0x00" for standard MP5424-0000, "0x01" for MP5424-0001)

24

ID2

MTP revision number (MTP revision number is stored here in case the user has to update the MTP)

25

CRC

Checksum of MTP registers 0x00 to 0x24. While writing the I2C register data to the MTP, the PMIC initiates a

checksum of all the related I2C registers and writes the result in this byte. During start-up, the PMIC calculates and

compares the MTP data with the 0x25 register’s content. If they match, the MTP data is loaded to the I2C register;

otherwise, the I2C register ignores the MTP data and uses the default setting.