M58LR128KB datasheet(38/110 Pages) NUMONYX

38 / 110 page

Configuration Register

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

38/111

Configuration Register

The Configuration Register configures the type of bus access that the memory performs.

Refer to Section 7: Read modes for details on read operations.

The Configuration Register is set through the command interface using the Set

Configuration Register command. After a reset or power-up the device is configured for

asynchronous read (CR15 = 1). The Configuration Register bits are described in Table 12

They specify the selection of the burst length, burst type, burst X latency and the read

operation. Refer to Figures 5 and 6 for examples of synchronous burst configurations.

6.1

Read select bit (CR15)

The read select bit, CR15, switches between asynchronous and synchronous read

operations.

When the read select bit is set to ’1’, read operations are asynchronous, and when the read

select bit is set to ’0’, read operations are synchronous.

Synchronous burst read is supported in both parameter and main blocks and can be

performed across banks.

On reset or power-up the read select bit is set to ’1’ for asynchronous access.

6.2

X latency bits (CR13-CR11)

The X latency bits are used during synchronous read operations to set the number of clock

cycles between the address being latched and the first data becoming available. Refer to

Figure 5: X latency and data output configuration example.

For correct operation the X latency bits can only assume the values in Table 12:

Configuration Register.

Table 11 shows how to set the X latency parameter, taking into account the speed class of

the device and the frequency used to read the Flash memory in synchronous mode.

Table 11.

X latency settings

fmax

tKmin

X latency min

30 MHz

33 ns

40 MHz

25 ns

54 MHz

19 ns

66 MHz

15 ns

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