M58LR128KB datasheet(27/110 Pages) NUMONYX

27 / 110 page

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

Command interface

27/111

If a Program command is issued during a block erase suspend, the erase operation cannot

be resumed until the program operation has completed.

The Program/Erase Suspend command does not change the read mode of the banks. If the

suspended bank was in read Status Register, read electronic signature or read CFI query

mode, the bank remains in that mode and outputs the corresponding data.

Refer to Section 8: Dual operations and multiple bank architecture for detailed information

about simultaneous operations allowed during Program/Erase Suspend.

During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip

Enable to VIH. Program/erase is aborted if Reset, RP, goes to VIL.

See Appendix C, Figure 21: Program suspend and resume flowchart and pseudocode, and

Figure 23: Erase suspend and resume flowchart and pseudocode for flowcharts for using

the Program/Erase Suspend command.

4.12

Program/Erase Resume command

The Program/Erase Resume command restarts the program or erase operation suspended

by the Program/Erase Suspend command. One bus write cycle is required to issue the

command. The command can be issued to any address.

The Program/Erase Resume command does not change the read mode of the banks. If the

suspended bank was in read Status Register, read electronic signature or read CFI query

mode the bank remains in that mode and outputs the corresponding data.

If a program command is issued during a block erase suspend, then the erase cannot be

resumed until the program operation has completed.

See Appendix C, Figure 21: Program suspend and resume flowchart and pseudocode, and

Figure 23: Erase suspend and resume flowchart and pseudocode for flowcharts for using

the Program/Erase Resume command.

4.13

Protection Register Program command

The Protection Register Program command programs the user OTP segments of the

Protection Register and the two Protection Register locks.

The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as

shown in Figure 4: Protection Register memory map.

The segments are programmed one word at a time. When shipped all bits in the segment

are set to ‘1’. The user can only program the bits to ‘0’.

Two bus write cycles are required to issue the Protection Register Program command.

●

The first bus cycle sets up the Protection Register Program command.

●

The second latches the address and data to be programmed to the Protection Register

and starts the Program/Erase Controller.

Read operations to the bank being programmed output the Status Register content after the

program operation has started.

Attempting to program a previously protected Protection Register results in a Status

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