M58LR128KB datasheet(25/110 Pages) NUMONYX

25 / 110 page

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

Command interface

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The Buffer Enhanced Factory Program Command consists of three phases: the setup

phase, the program and verify phase, and the exit phase, Please refer to Table 7: Factory

commands for detailed information.

4.10.1

Setup phase

The Buffer Enhanced Factory Program command requires two bus write cycles to initiate the

command:

●

The first bus write cycle sets up the Buffer Enhanced Factory Program command.

●

The second bus write cycle confirms the command.

After the confirm command is issued, read operations output the contents of the Status

to program.

The Status Register P/EC bit SR7 should be read to check that the P/EC is ready to

proceed to the next phase.

If an error is detected, SR4 goes high (set to ‘1’) and the Buffer Enhanced Factory Program

operation is terminated. See Section 5: Status Register for details on the error.

4.10.2

Program and verify phase

The program and verify phase requires 32 cycles to program the 32 words to the write

buffer. The data is stored sequentially, starting at the first address of the write buffer, until the

write buffer is full (32 words). To program less than 32 words, the remaining words should be

programmed with FFFFh.

Three successive steps are required to issue and execute the program and verify phase of

the command:

Use one bus write operation to latch the start address and the first word to be

programmed. The Status Register bank write status bit SR0 should be read to check

that the P/EC is ready for the next word.

Each subsequent word to be programmed is latched with a new bus write operation.

The address must remain the start address as the P/EC increments the address

location. If any address is given that is not in the same block as the start address, the

program and verify phase terminates. Status Register bit SR0 should be read between

each bus write cycle to check that the P/EC is ready for the next word.

Once the write buffer is full, the data is programmed sequentially to the memory array.

After the program operation the device automatically verifies the data and reprograms if

necessary.

The program and verify phase can be repeated, without re-issuing the command, to

program additional 32 word locations as long as the address remains in the same block.

Finally, after all words, or the entire block have been programmed, write one bus write

operation to any address outside the block containing the start address, to terminate

program and verify phase.

Status Register bit SR0 must be checked to determine whether the program operation is

finished. The Status Register may be checked for errors at any time but it must be checked

after the entire block has been programmed.

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