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M58LR128KB 数据表(PDF) 41 Page - Numonyx B.V |
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M58LR128KB 数据表(HTML) 41 Page - Numonyx B.V |
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41 / 110 page  M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Configuration Register 41/111 Table 12. Configuration Register Bit Description Value Description CR15 Read select 0 Synchronous read 1 Asynchronous Read (default at power-on) CR14 Reserved CR13-CR11 X latency 010 2 clock latency(1) 1. The combination X latency=2, data held for two clock cycles and Wait active one data cycle before the WAIT state is not supported. 011 3 clock latency 100 4 clock latency 101 5 clock latency 110 6 clock latency 111 7 clock latency (default) Other configurations reserved CR10 Wait polarity 0 WAIT is active Low 1 WAIT is active High (default) CR9 Data output configuration 0 Data held for one clock cycle 1 Data held for two clock cycles (default)(1) CR8 Wait configuration 0 WAIT is active during WAIT state 1 WAIT is active one data cycle before WAIT state(1) (default) CR7 Burst type 0Reserved 1 Sequential (default) CR6 Valid Clock edge 0 Falling Clock edge 1 Rising Clock edge (default) CR5-CR4 Reserved CR3 Wrap burst 0Wrap 1 No wrap (default) CR2-CR0 Burst Length 001 4 words 010 8 words 011 16 words 111 Continuous (default) |
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