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M58LR128KB 数据表(PDF) 17 Page - Numonyx B.V

部件名 M58LR128KB
功能描述  128 or 256 Mbit (횞16, multiple bank, multilevel interface, burst) 1.8 V supply Flash memories
PDF  110 Pages
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制造商  NUMONYX [Numonyx B.V]
网页  http://www.numonyx.com
标志 NUMONYX - Numonyx B.V

M58LR128KB 数据表(HTML) 17 Page - Numonyx B.V

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M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB
Bus operations
17/111
3.5
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power
consumption is reduced to the standby level IDD3 and the outputs are set to high impedance,
independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH
during a program or erase operation, the device enters standby mode when finished.
3.6
Reset
During reset mode the memory is deselected and the outputs are high impedance. The
memory is in reset mode when Reset is at VIL. The power consumption is reduced to the
reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If
Reset is pulled to VSS during a program or erase, this operation is aborted and the memory
content is no longer valid.
Table 4.
Bus operations(1)
1.
X = ‘don't care’
Operation
E
G
W
L
RP
WAIT(2)
2.
WAIT signal polarity is configured using the Set Configuration Register command.
DQ15-DQ0
Bus read
VIL
VIL
VIH
VIL
(3)
3.
L can be tied to VIH if the valid address has been previously latched.
VIH
Data output
Bus write
VIL
VIH
VIL
VIL
(3)
VIH
Data input
Address latch
VIL
XVIH
VIL
VIH
Data output or Hi-Z(4)
4.
Depends on G.
Output disable
VIL
VIH
VIH
XVIH
Hi-Z
Hi-Z
Standby
VIH
XX
X
VIH
Hi-Z
Hi-Z
Reset
X
X
X
X
VIL
Hi-Z
Hi-Z



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