数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

M58LR128KB 数据表(PDF) 16 Page - Numonyx B.V

部件名 M58LR128KB
功能描述  128 or 256 Mbit (횞16, multiple bank, multilevel interface, burst) 1.8 V supply Flash memories
PDF  110 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  NUMONYX [Numonyx B.V]
网页  http://www.numonyx.com
标志 NUMONYX - Numonyx B.V

M58LR128KB 数据表(HTML) 16 Page - Numonyx B.V

Back Button M58LR128KB Datasheet HTML 12Page - Numonyx B.V M58LR128KB Datasheet HTML 13Page - Numonyx B.V M58LR128KB Datasheet HTML 14Page - Numonyx B.V M58LR128KB Datasheet HTML 15Page - Numonyx B.V M58LR128KB Datasheet HTML 16Page - Numonyx B.V M58LR128KB Datasheet HTML 17Page - Numonyx B.V M58LR128KB Datasheet HTML 18Page - Numonyx B.V M58LR128KB Datasheet HTML 19Page - Numonyx B.V M58LR128KB Datasheet HTML 20Page - Numonyx B.V Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 110 page
background image
Bus operations
M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB
16/111
3
Bus operations
There are six standard bus operations that control the device. These are bus read, bus
write, address latch, output disable, standby and reset. See Table 4: Bus operations for a
summary.
Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus write operations.
3.1
Bus read
Bus read operations are used to output the contents of the memory array, the electronic
signature, the Status Register and the Common Flash interface. Both Chip Enable and
Output Enable must be at VIL to perform a read operation. The Chip Enable input should be
used to enable the device, and Output Enable should be used to gate data onto the output.
The data read depends on the previous command written to the memory (see command
interface section). See Figures 9, 10 and 11 read AC waveforms, and Tables 24 and 25 read
AC characteristics for details of when the output becomes valid.
3.2
Bus write
Bus write operations write commands to the memory or latch input data to be programmed.
A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output
Enable at VIH. Commands, input data and addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to the
write operation by toggling Latch Enable (when Chip Enable is at VIL). The Latch Enable
must be tied to VIH during the bus write operation.
See Figures 15 and 16, write AC waveforms, and Tables 26 and 27, write AC characteristics
for details of the timing requirements.
3.3
Address Latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must be
at VIL during address latch operations. The addresses are latched on the rising edge of
Latch Enable.
3.4
Output disable
The outputs are high impedance when the Output Enable is at VIH.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com