ST52T400 datasheet(22/94 Pages) STMICROELECTRONICS

22 / 94 page

ST52T400/T440/E440/T441

22/94

2.2.1 Ram and Stack.

RAM consists of 128 (G0/G1/F0/F1 types) or 256

(G2/G3/F2/F3 types) general purpose 8-bit regis-

ters.

All the registers in RAM can be specified by using

a decimal address, e.g. 0 identifies the first regis-

ter of RAM.

To read or write in the RAM registers, the LOAD

instructions must be used (see Table 2.5).

When the instructions like Interrupt request or

CALL are executed, a STACK is used to push the

PC. The STACK is push directly in the RAM. For

each level of stack 2 bytes of RAM are used. The

values of this stack are stored from the last RAM

stack must be less than 128. When a subroutine

call or interrupt request occurs, the contents of

each level is shifted into the next level while the

content of the PC is shifted into the first level.

When a subroutine or interrupt return occurs (RET

or RETI instructions), the first level register is

shifted back into the PC and the value of each

level is popped back into the previous level. These

operating modes are illustrated in Figure 2.5.

2.2.2 Input Registers Bench.

The Input Registers (IR) bench consists of 20 8-bit

registers containing data deriving from the periph-

erals and parallel ports.

All the registers can be specified by using a deci-

mal address, e.g. 0 identifies the first register of

the IR.

The assembler instruction:

LDRI reg,inp_teg loads

the value in the

inp IR to the register (RAM loca-

tion) identified by the address reg.

The first input register is dedicated to store the

value of the stack pointer. The next 12 registers of

the IR are dedicated to the 6 (for ST52X440G/

441G) or the 4 converted values (for ST52X440F/

441F) in case of converted values coming from

the Analog Comparator (in ST52x400 devices

these registers are not used). Each of these val-

ues are stored on two bytes because of the reso-

lution of the A/D conversion process. The last 7

registers contain data from the I/O ports and

PWM/Timers.

Table

2.1

summarizes

the

address and the relative peripheral. In order to

simplify

the

concept

mnemonic

name

assigned to the registers. The same name is used

in VISUAL FIVE development tools.

Figure 2.5 Stack Operation

PROGRAM COUNTER

RAM

REG 0

REG 1

REG 2

REG 3

REG 4

REG 5

REG 255

REG 254

REG 253

REG 252

STACK LEVEL 1

STACK LEVEL 2

..........................

STACK LEVEL n

WHEN CALL OR

INTERRUPT REQ.

WHEN RETI OR RET

OCCURS

Stack

Pointer

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