ST52T400 datasheet(33/94 Pages) STMICROELECTRONICS

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ST52T400/T440/E440/T441

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3 EPROM PROGRAMMING

EPROM memory provides an on-chip user-pro-

grammable non-volatile memory, which allows fast

and reliable storage of user data.

EPROM memory can be locked by the user. In

fact, a memory location, called Lock Cell, is

devoted to lock the EPROM and to prevent

memory reading. A software identification code

(max 64 bytes), called ID CODE may also be writ-

ten in order to distinguish which software version

is stored in the memory.

There are 64 kbits of memory space with an 8-bit

internal parallelism (8 kbytes) addressed by a 13-

bit bus. The data bus is of 8 bits.

Memory has a double supply: VPP is equal to

12V

±5% in Programming Phase or to V

SS during

Working Phase. VDD is equal to 5V±10%.

The

ST52x400/440/441

EPROM

memory

divided into three main blocks (see Figure 3.1):

•

Interrupt Vectors memory block (3 through 14)

contains the addresses for the interrupt rou-

tines. Each address is composed of three

bytes.

•

Mbfs Setting memory block (15 through 1024)

contains the coordinates of the vertexes of

every Mbf defined in the program. If this part of

the memory is not used to store the Mbfs set-

ting, it can be use to store the instruction set on

the user program.

•

The Program Instruction Set memory block

(1024 through 8191) contains the instruction

set of the user program.

Table 3.1 EPROM Control Register

OPERATION

Stand By

Memory

Reading / Verify

Memory Unlock and

Lock Status Reading

Memory

Writing

Memory

Lock

ID CODE

Writing

Memory Lock Status

Reading / Verify

ID CODE

Reading / Verify

Figure 3.1 Program Memory Organization

RESET VECTOR

INTERRUPT VECTORS

MEMBERSHIP FUNCTIONS

PARAMETERS

PROGRAM INSTRUCTIONS

AND PERMANENT DATA

PROGRAM INSTRUCTIONS

AND PERMANENT DATA

0000h

0015h

0400h

0003h

2000h

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