ST52T400 datasheet(30/94 Pages) STMICROELECTRONICS

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ST52T400/T440/E440/T441

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2.4 Arithmetic Logic Unit

ST52x400/440/441 supplies 46 instructions that

perform computations and control the device.

Computational time required for each instruction

consists of one clock pulse for each Cycle plus 2

clock pulses for the decoding phase. Total compu-

tation time for each instruction is reported in Table

2.5

The ALU of the ST52x400/440/441 can perform

multiplication (MULT) and division (DIV). Multipli-

cation is performed by using 8 bit operands stor-

ing the result in 2 registers (16 bit values).

Division is performed between a 16 bit dividend

and an 8 bit divider, the result and the remainder

are stored in two 8-bit registers.

WARNING:

If the LSB of the multiplication result

is 0, the Zero flag is set although the result is not

2.4.1 Addressing Modes.

ST52x400/440/441 instructions allow the following

addressing modes:

Inherent: this instruction type does not require an

operand because the opcode specifies all the

information necessary to carry out the instruction.

Examples: NOP, RET.

Immediate: these instructions have an operand as

a source immediate value. Examples: LDRC,

PGSET.

Direct: the operands of these instructions are

specified with the direct addresses. The operands

can refer, according to the opcode, to addresses

belonging to the different addressing spaces.

Example: SUB, LDRE.

Indirect: data addresses that are required are

found in the locations specified as operands. Both

source

and/or

destination

operands

can

addressed indirectly. The operands can refer,

(according to the opcode) to addresses belonging

to different addressing spaces. Examples: LDRE

(reg1),(reg2).

2.4.2 Instruction Types.

ST FIVE supplies the following instruction types:

Load Instructions

Arithmetic and Logic Instructions

Jump Instructions

Interrupt Management Instructions

Control Instructions

The instructions are listed in Table 2.5, Table 2.6

and Table 2.7.

Table 2.5 Arithmetic & Logic Instruction Set

Load Instructions

Mnemonic

Instruction

Bytes

Cycles

LDCE

LDCE confx,memx

LDCR

LDRC confx,regx

LDFR

LDFR fuzzyx,regx

LDPE

LDPE outx,memx

LDPE

LDPE outx,(regx)

LDPR

LDPR outx,regx

LDRC

LDRC regx,const

LDRE

LDRE regx,memx

LDRE

LDRE (regx),(regy)

LDRI

LDRI regx,inpx

LDRR

LDRR regx, regy

PGSET

PGSET const

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