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ST52T400 数据表(PDF) 40 Page - STMicroelectronics |
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ST52T400 数据表(HTML) 40 Page - STMicroelectronics |
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40 / 94 page ![]() ST52T400/T440/E440/T441 40/94 4.5 Interrupt Priority Seven priority levels are available: level 6 has the lowest priority, level 0 has the highest priority. Level 6 is associated to the Main Program, levels 5 to 1 are programmable by means of the priority registers called REG_CONF17 and REG_CONF18; whereas the higher level is related to the External Interrupt (INT_EXT). PWM/Timer, TRIAC/PWM and Analog Block are identified by a three-bit Peripheral Code (see Table 4.2); in order to set the i-th priority level the user must write the peripheral label i in the related INT i priority level. For instance: LDRC 10,193 (loads the value 193=’11000001’ in the RAM Register 10) LDRC 11,168 (loads the value 168=’10101000’ in the RAM Register 11) LDCR 17,10 (REG_CONF17= ‘11000001’) LDCR 18,11 (REG_CONF18= ‘10101000’) thus defining the following priority levels: s Level 1: INT_PWM/TIMER (PWM/TIMER Code: 001) s Level 2: INT_ADC (ADC Code: 000) s Level 3: INT_TRIAC/PWM_R (TRIAC/PWM Code: 011) s Level 4: INT_TRIAC/Ph (TRIAC/Ph Code: 100) s Level 5: INT_TRIAC/PWM_F (TRIAC/PWM_F Code: 010) REMARK: The Interrupt priority must be set at the beginning of the main program, because at the RESET REG_CONF1=’00000000’, this condition could generate wrong operations. Further, changing the priority levels must be avoided in interrupt service routines. When a source provides an Interrupt request, and the request processing is also enabled, the CU changes the normal sequential flow of a program by transferring program control to a selected ser- vice routine. When an interrupt occurs the CU executes a JUMP instruction to the address loaded in the related location of the Interrupt Vector and the flags are saved. When the execution returns to the original pro- Figure 4.5 Interrupt Configuration Registers 17 and 18 D0 D1 D2 D3 D4 D5 D6 D7 INT 1 Not Used INT 2 REG_CONF17 Interrupts Priority D8 D9 D10 D11 D12 D13 D14 D15 REG_CONF18 INT 3 INT 5 INT 4 Table 4.3 Conf. Registers 17-18 Description Bit Name Value Level 0, 1, 2 INT1 Peripheral High 3, 4, 5 INT2 Peripheral MediumHigh 6, 7, 8 INT4 Peripheral MediumLow 9, 10, 11 INT5 Peripheral Low 12, 13, INT6 Peripheral Very Low |
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