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ST52T400 数据表(PDF) 55 Page - STMicroelectronics

部件名 ST52T400
功能描述  8-BIT INTELLIGENT CONTROLLER UNIT ICU Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG
PDF  94 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST52T400 数据表(HTML) 55 Page - STMicroelectronics

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8.2 Register Description
WDT Timeout period can be set by setting the first
4 bits of REG_CONF2: this allows 16 different val-
ues of WDT Clock pulse number to be defined.
The WDT CLK is derived from the Master Clock
divided by 500. Timeout is then obtained by multi-
plying the WDT CLK period for the number of
pulses
defined
in
configuration
register
REG_CONF2. Table 8.4 illustrates the pulse
length for typical values of Master Clock.
Table 8.3 illustrates the timeout WDT values when
Master Clock is 5 MHz.
Table 8.2 WDT REG_CONF2
Bit
Name
Value
Timeout Values (WDT
CLK pulses)
0
D(3:0)
0000
1
0001
625
0010
1250
0011
1875
1
0100
2500
0101
3125
0110
3750
0111
4375
2
1000
5000
1001
5625
1010
6250
1011
6875
3
1100
7500
1101
8125
1110
8750
1111
9375
4-7
NC
x
Not Used
Reset Configuration ‘0000’
Table 8.3 Timeout Values with CLKM=5 MHz
Bit
Name
Value
Timeout Values
0
D(3:0)
0000
0.1
0001
62.5
0010
125
0011
187.5
1
0100
250
0101
312.5
0110
375
0111
437.5
2
1000
500
1001
562.5
1010
625
1011
687.5
3
1100
750
1101
812.5
1110
875
1111
937.5
4-7
NC
x
Not Used
Reset Configuration ‘0000’
Table 8.4 Typical WDT CLK PERIOD
MASTER CLK
(MHz)
WDT CLK
(KHz)
WDT CLK
PERIOD (ms)
4
8
0.125
510
0.1
8
16
0.0625
10
20
0.05
20
40
0.025



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