ST52T400 datasheet(35/94 Pages) STMICROELECTRONICS

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ST52T400/T440/E440/T441

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INC_ADD (PB1) signal increments the memory

address.Control Register. When RST_CONF is

high, the DATA I/O Port A is in output, other-

wise it is always in input.

The signal applied on INC_CONF (PB3) incre-

ments the EPROM Control Register value. To

select the operation it must be provided as many

signal edges as the value to be written in the reg-

ister (see Table 3.1).

The signal on PHASE (PB7) validates the opera-

tion selected by means of the EPROM Control

3.1.1 EPROM Operation. In order to execute an

EPROM operation (see Table 3.1), the corre-

sponding identification value must be loaded in

the EPROM Control Register. The signal timing is

the following: RST_ADD= high and PHASE= high,

RST_CONF changes from low to high level, to

reset

the

EPROM

Control

and

INC_CONF signal generates a number of positive

pulses equal to the value to be loaded. After this

sequence, a negative pulse of the PHASE signal

will validate the selected operation. The minimum

PHASE signal pulse width must be 10

µsfor the

EPROM Writing Operation and 100 ns for the oth-

ers.

When RST_CONF is high, the DATA I/O Port A is

enabled in output and the reading/verify operation

results are available.

After a writing operation, when RST_CONF is

high, Port A is in output without valid data.

3.1.2 EPROM Locking. The Memory Lock oper-

ation, which is identified with the number 4 in the

EPROM Control Register, writes “0" in the Mem-

ory Lock Cell.

At the beginning of an External Operation, when

RST_ADD signal changes from low level to high

level, the Memory Lock Status flag is “0", therefore

it is necessary to unlock it before proceeding.

In order to unlock the Memory Lock Status flag the

operation, which is identified with the number 2 in

the EPROM Control Register must be executed

(see Figure 3.2).

The Memory Lock Status flag can be changed.

Therefore, after a Memory Lock operation, exter-

nal operations cannot be executed except reading

(or verify) the OTP Code and the Memory Lock

Status.

3.1.3 EPROM Writing. When

the

memory

blank, all the bits are at logic level “1". The data is

introduced by programming only the zeros in the

desired memory location; however, all input data

must contain both ”1” and “0". The only way to

change “0" into ”1” is to erase the whole memory

(by exposure to UV light) and reprogram it.

The memory is in Writing mode when the EPROM

Control Register value is 3.

The VPP voltage must be 12V±5%, with stable

data on the data bus PB(0:7). The signals timing is

the following (see Figure 3.2):

1) RST_ADD and RST_CONF change from low to

high level,

2) two pulses on INC_CONF signal load the Mem-

ory Unlock operation code,

3) a negative pulse (100 ns) on the PHASE signal

validates the Memory Unlock operation,

4) a negative pulse on RST_CONF signal resets

the EPROM Control Register,

5) three positive pulses on INC_CONF load the

Memory Writing operation code,

6) a train of positive pulses on INC_ADD signal

increments the memory location address up to the

requested value (generally this is a sequential

operation and only one pulse is used),

7) a negative pulse (10

µs) on the PHASE signal

validates the Memory Writing operation.

3.1.4

EPROM Reading/Verify Margin Mode.

Thereadingphaseis executed withVPP=5V±5%,

instead of verify phase that needs VPP=12V±5%.

The Memory Verify operation is available in order

to verify the correctness of the data written. The

Memory Verify Margin Mode operation may be

executed immediately after the writing of each

byte and in this case (see Figure 3.2):

1) one positive pulse on RST_CONF signal resets

the Control Register, if it was not already reset

2) one positive pulse on INC_CONF loads the

Memory Reading/Verify operation code,

3) one negative pulse (100 ns) on the PHASE sig-

nal validates the Memory Reading/Verify opera-

tion,

4) a negative pulse on RST_CONF signal puts in

the PB(0:7) port the value stored in the actual

memory address and resets the EPROM Control

Then, if any error in writing occurred, the user has

to repeat the EPROM writing.

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