STR910FAM32 datasheet(53/101 Pages) STMICROELECTRONICS

53 / 101 page

STR91xFAx3x, STR91xFAx4x

Memory mapping

53/101

Memory mapping

The ARM966E-S CPU addresses a single linear address space of 4 giga-bytes (232) from

address 0x0000.0000 to 0xFFFF.FFFF as shown in Figure 9. Upon reset the CPU boots

from address 0x0000.0000, which is chip-select zero at address zero in the Flash Memory

Interface (FMI).

The Instruction TCM and Data TCM enable high-speed CPU operation without incurring any

performance or power penalties associated with accessing the system buses (AHB and

APB). I-TCM and D-TCM address ranges are shown at the bottom of the memory map in

Figure 9.

6.1

Buffered and non-buffered writes

The CPU makes use of write buffers on the AHB and the D-TCM to decouple the CPU from

any wait states associated with a write operation. The user may choose to use write with

buffers on the AHB by setting bit 3 in control register CP15 and selecting the appropriate

AHB address range when writing. By default at reset, buffered writes are disabled (bit 3 of

CP15 is clear) and all AHB writes are non-buffered until enabled. Figure 9 shows that most

addressable items on the AHB are aliased at two address ranges, one for buffered writes

and another for non-buffered writes. A buffered write will allow the CPU to continue program

execution while the write-back is performed through a FIFO to the final destination on the

AHB. If the FIFO is full, the CPU is stalled until FIFO space is available. A non-buffered write

will impose an immediate delay to the CPU, but results in a direct write to the final AHB

destination, ensuring data coherency. Read operations from AHB locations are always direct

and never buffered.

6.2

System (AHB) and peripheral (APB) buses

The CPU will access SRAM, higher-speed peripherals (USB, Ethernet, Programmable

DMA), and the external bus (EMI) on the AHB at their respective base addresses indicated

in Figure 9. Lower-speed peripherals reside on the APB and are accessed using two

separate AHB-to-APB bridge units (APB0 and APB1). These bridge units are essentially

address windows connecting the AHB to the APB. To access an individual APB peripheral,

the CPU will place an address on the AHB bus equal to the base address of the appropriate

bridge unit APB0 or APB1, plus the offset of the particular peripheral, plus the offset of the

individual data location within the peripheral. Figure 9 shows the base addresses of bridge

units APB0 and APB1, and also the base address of each APB peripheral. Please consult

the STR91xFA Reference manual for the address of data locations within each individual

peripheral.

6.3

SRAM

The SRAM is aliased at three separate address ranges as shown in Figure 9. When the

CPU accesses SRAM starting at 0x0400.0000, the SRAM appears on the D-TCM. When

CPU access starts at 0x4000.0000, SRAM appears in the buffered AHB range. Beginning at

CPU address 0x5000.0000, SRAM is in non-buffered AHB range. The SRAM size must be

specified by CPU intitialization firmware writing to a control register after any reset condition.

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