STR910FAM32 datasheet(22/101 Pages) STMICROELECTRONICS

22 / 101 page

Functional overview

STR91xFAx3x, STR91xFAx4x

22/101

3.10.6

Baud rate clock (BRCLK)

The baud rate clock is an internal clock derived from fMSTR that is used by the three on-chip

UART peripherals for baudrate generation and to generate the SSPCLK to drive the two

SSP peripherals. The frequency can be optionally divided by 2.

3.10.7

External memory interface bus clock (BCLK)

The BCLK is an internal clock that controls the EMI bus. All EMI bus signals are

synchronized to the BCLK. The BCLK is derived from the HCLK and the frequency can be

configured to be the same or half that of the HCLK. Refer to Table 17 on page 65 for the

maximum BCLK frequency (fBCLK). The BCLK clock is available on the LFBGA package as

an output pin.

3.10.8

USB interface clock

Special consideration regarding the USB interface: The clock to the USB interface must

operate at 48 MHz and comes from one of three sources, selected under firmware control:

●

CCU master clock output of 48 MHz.

●

CCU master clock output of 96 MHz. An optional divided-by-two circuit is available to

produce 48 MHz for the USB while the CPU system runs at 96MHz.

●

STR91xFA pin P2.7. An external 48 MHz oscillator connected to pin P2.7 can directly

source the USB while the CCU master clock can run at some frequency other than 48

or 96 MHz.

3.10.9

Ethernet MAC clock

Special consideration regarding the Ethernet MAC: The external Ethernet PHY interface

device requires it’s own 25 MHz clock source. This clock can come from one of two sources:

●

A 25 MHz clock signal coming from a dedicated output pin (P5.2) of the STR91xFA. In

this case, the STR91xFA must use a 25 MHz signal on its main oscillator input in order

to pass this 25 MHz clock back out to the PHY device through pin P5.2. The advantage

here is that an inexpensive 25 MHz crystal may be used to source a clock to both the

STR91xFA and the external PHY device.

●

An external 25 MHz oscillator connected directly to the external PHY interface device.

In this case, the STR91xFA can operate independent of 25 MHz.

3.10.10

External RTC calibration clock

The RTC_CLK can be enabled as an output on the JRTCK pin. The RTC_CLK is used for

RTC oscillator calibration. The RTC_CLK is active in Sleep mode and can be used as a

system wake up control clock.

3.10.11

Operation example

As an example of CCU operation, a 25 MHz crystal can be connected to the main oscillator

input on pins X1_CPU and X2_CPU, a 32.768 kHz crystal connected to pins X1_RTC and

X2_RTC, and the clock input of an external Ethernet PHY device is connected to STR91xFA

output pin P5.2. In this case, the CCU can run the CPU at 96 MHz from PLL, the USB

interface at 48 MHz, and the Ethernet interface at 25 MHz. The RTC is always running in the

background at 32.768 kHz, and the CPU can go to very low power mode dynamically by

running from 32.768 kHz and shutting off peripheral clocks and the PLL as needed.

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