STR910FAM32 datasheet(38/101 Pages) STMICROELECTRONICS

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Functional overview

STR91xFAx3x, STR91xFAx4x

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high data bytes respectively. The output signal EMI_RDn is the read strobe for both the

low and high data bytes.

●

8-bit multiplexed data mode: This is a variant of the 16-bit multiplexed mode.

Although this mode can provide 24 bits of address and 8 bits of data, it does require an

external latch device on Port 8. However, this mode is most efficient when connecting

devices that only require 8 bits of address on an 8-bit multiplexed address/data bus,

and have simple read, write, and latch inputs as shown in Figure 5

To use all 24 address bits, the following applies: 8 bits of lowest-order data and 8 bits of

lowest-order address are multiplexed on port 8. On port 9, 8-bits of mid-order address are

multiplexed with 8 bits of data, but these 8 data values are always at logic zero on this port

during a write operation, and these 8 data bits are ignored during a read operation. An

external latch device is needed to de-multiplex the mid-order 8 address bits that are

generated on port 8. Port 7 outputs the 8 highest-order address signals directly (not

multiplexed). The output signal on pin EMI_ALE is used to demultiplex the signals on ports 8

and 9, and the polarity of EMI_ALE is programmable. The output signal on pin

EMI_BWR_WRLn is the data write strobe, and the output on pin EMI_RDn is the data read

strobe.

●

8-bit non-multiplexed data mode (Figure 6): Eight bits of data are on port 8, while 16

bits of address are output on ports 7 and 9. The output signal on pin EMI_BWR_BWLn

is the data write strobe and the output on pin EMI_RDn is the data read strobe.

●

Burst Mode Support (LFBGA package only): The EMI bus supports synchronized

burst read and write bus cycle in multiplexed and non-multiplexed mode. The additional

EMI signals in the LFBGA package that support the burst mode are:

–

EMI_BCLK -the bus clock output. The EMI_BCLK has the same frequency or half

of that of the HCLK and can be disabled by the user

–

EMI_WAITn - the not ready or wait input signal for synchronous access

–

EMI_BAAn - burst address advance or burst enable signal

–

EMI_WEn - write enable signal

–

EMI_UBn, EMI_LBn - upper byte and lower byte enable signals. These two signals

share the same pins as the EMI_WRLn and EMI_WRHn and are user configurable

through the EMI register.

By defining the bus parameters such as burst length, burst type, read and write timings

in the EMI control registers, the EMI bus is able to interface to standard burst memory

devices. The burst timing specification and waveform will be provided in the next data

sheet release

STR910FAM32 数据表(PDF) 38 Page - STMicroelectronics

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