STR910FAM32 datasheet(37/101 Pages) STMICROELECTRONICS

37 / 101 page

STR91xFAx3x, STR91xFAx4x

Functional overview

37/101

The IMC unit has the following features:

●

Three PWM outputs generated using a 10 or 16-bit PWM counter, one for each phase

U, V, W. Complimentary PWM outputs are also generated for each phase.

●

Choice of classic or zero-centered PWM generation modes

●

10 or 16-bit PWM counter clock is supplied through a programmable 8-bit prescaler of

the APB clock.

●

Programmable 6 or 10-bit dead-time generator to add delay to each of the three

complimentary PWM outputs

●

8-bit repetition counter

●

Automatic rotor speed measurement with 16-bit resolution. Schmitt trigger tachometer

input with programmable edge detection

●

Hardware asynchronous emergency stop input

●

A dedicated interrupt to CPU with eight flags

●

Enhanced Motor stop output polarity configuration

●

Double update option when PWM counter reaches the max and min values in Zero-

centered mode

●

Locking feature to prevent some control register bits from being advertently modified

●

Trigger output to start an ADC conversion

3.27

External memory interface (EMI)

STR91xFA devices in 128-pin and 144-ball packages offer an external memory bus for

connecting external parallel peripherals and memories. The EMI bus resides on ports 7, 8,

and 9 and operates with either an 8 or 16-bit data path. The configuration of 8 or 16 bit

mode is specified by CPU firmware writing to configuration registers at run-time. If the

application does not use the EMI bus, then these port pins may be used for general purpose

I/O as shown in Table 8.

The EMI has the following features:

●

Supports static asynchronous memory access cycles, including page mode for non-

mux operation. The bus control signals include:

–

EMI_RDn - read signal, x8 or x16 mode

–

EMI_BWR_WRLn - write signal in x8 mode and write low byte signal in x16 mode

–

EMI_WRHn - write high byte signal in x16 mode

–

EMI_ALE - address latch signal for x8 or x16 mux bus mode with programmable

polarity

●

Four configurable memory regions, each with a chip select output (EMI_CS0n ...

EMI_CS3n)

●

Programmable wait states per memory region for both write and read operations

●

16-bit multiplexed data mode (Figure 4): 16 bits of data and 16 bits of low-order

address are multiplexed together on ports 8 and 9, while port 7 contains eight more

high-order address signals. The output signal on pin EMI_ALE is used to demultiplex

the signals on ports 8 and 9, and the polarity of EMI_ALE is programmable. The output

signals on pins EMI_BWR_WRLn and EMI_WRHn are the write strobes for the low and

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