STR910FAM32 datasheet(12/101 Pages) STMICROELECTRONICS

12 / 101 page

Functional overview

STR91xFAx3x, STR91xFAx4x

12/101

Functional overview

3.1

System-in-a-Package (SiP)

The STR91xFA is a SiP device, comprised of two stacked die. One die is the ARM966E-S

CPU with peripheral interfaces and analog functions, and the other die is the burst Flash.

The two die are connected to each other by a custom high-speed 32-bit burst memory

interface and a serial JTAG test/programming interface.

3.2

Package choice

STR91xFA devices are available in 128-pin (14 x 14 mm) and 80-pin (12 x 12 mm) LQFP

and LFBGA144 (10 x 10 mm) packages. Refer to Table 2: Device summary on page 11 for a

list of available peripherals for each of the package choices.

3.3

ARM966E-S CPU core

The ARM966E-S core inherently has separate instruction and data memory interfaces

(Harvard architecture), allowing the CPU to simultaneously fetch an instruction, and read or

write a data item through two Tightly-Coupled Memory (TCM) interfaces as shown in

Figure 1. The result is streamlined CPU Load and Store operations and a significant

reduction in cycle count per instruction. In addition to this, a 5-stage pipeline is used to

increase the amount of operational parallelism, giving the most performance out of each

clock cycle.

Ten DSP-enhanced instruction extensions are supported by this core, including single-cycle

execution of 32x16 Multiply-Accumulate, saturating addition/subtraction, and count leading-

zeros.

The ARM966E-S core is binary compatible with 32-bit ARM7 code and 16-bit Thumb® code.

3.4

Burst Flash memory interface

A Burst Flash memory interface (Figure 1) has been integrated into the Instruction TCM

(I-TCM) path of the ARM966E-S core. Also in this path is an 8-instruction Pre-Fetch Queue

(PFQ) and a 15-entry Branch Cache (BC), enabling the ARM966E-S core to perform up to

96 MIPS while executing code directly from Flash memory. This architecture provides high

performance levels without a costly instruction SRAM, instruction cache, or external

SDRAM. Eliminating the instruction cache also means interrupt latency is reduced and code

execution becomes more deterministic.

3.4.1

Pre-Fetch Queue (PFQ)

As the CPU core accesses sequential instructions through the I-TCM, the PFQ always looks

ahead and will pre-fetch instructions, taking advantage any idle bus cycles due to variable

length instructions. The PFQ will fetch 32-bits at a time from the Burst Flash memory at a

rate of up to 96 MHz.

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