ST6369 datasheet(62/71 Pages) STMICROELECTRONICS

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PIN DESCRIPTION

VDD and VSS. Power is supplied to the MCU using

these two pins. VDD is power and VSS is the ground

connection.

OSCIN, OSCOUT. These pins are internally con-

nected to the on-chip oscillator circuit. A quartz

crystal or a ceramic resonator can be connected

between these two pins in order to allow the cor-

rect operation of the MCU with various stabil-

ity/cost trade-offs. The OSCIN pin is the input pin,

the OSCOUT pin is the output pin.

RESET. The active low RESET pin is used to start

the microcontroller to the beginning of its program.

Additionally the quartz crystal oscillator will be dis-

abled when the RESET pin is low to reduce power

consumption during reset phase.

TEST/VPP. The TEST pin must be held at VSS for

normal operation.

If this pin is connected to a +12.5V level during the

reset phase, The EPROM programming mode is

entered.

CAUTION: Exceeding 13V on TEST/VPP pin will

permanently damaged the device

PA0-PA7. These 8 lines are organized as one I/O

port (A). Each line may be configured as either an

input with or without pull-up resistor or as an output

under software control of the data direction regis-

ter. Pins PA4 to PA7 are configured as open-drain

outputs (12V drive). On PA4-PA7 pins the input

pull-up option is not available while PA6 and PA7

have additional current driving capability (25mA,

VOL:1V). PA0 to PA3 pins are configured as push-

pull.

PB1-PB2, PB4-PB6. These 5 lines are organized

as one I/O port (B). Each line may be configured as

either an input with or without internal pull-up resis-

tor or as an output under software control of the

data direction register.

PC0-PC7. These 8 lines are organized as one I/O

port (C). Each line may be configured as either an

input with or without internal pull-up resistor or as

an output under software control of the data direc-

tion register. Pins PC0 to PC3 are configured as

open-drain (5V drive) in output mode while PC4 to

PC7 are open-drain with 12V drive and the input

pull-up options does not exist on these four pins.

PC0, PC1 and PC3 lines when in output mode are

“ANDed” with the SPI control signals and are all

open-drain. PC0 is connected to the SPI clock sig-

nal (SCL), PC1 with the SPI data signal (SDA)

while PC3 is connected with SPI enable signal

(SEN, used in S-BUS protocol). Pin PC4 and PC6

can also be inputs to software programmable edge

sensitive latches which can generate interrupts;

PC4 can be connected to Power Interrupt while

PC6 can be connected to the HSYNC/NMI inter-

rupt line.

DA0-DA5. These pins are the six PWM D/A out-

puts of the 6-bit on-chip D/A converters. These

lines have open-drain outputs with 12V drive. The

output repetition rate is 31.25KHz (with 8MHz

clock).

AD. This is the input of the on-chip 10 levels com-

parator that can be used to implement the Analog

Keyboard function. This pin is an high impedance

input able to withstand signals with a peak ampli-

tude up to 12V.

VSYNC. This is the Vertical Synchronization pin.

This pin is connected to an internal timer interrupt.

O0, O1. These two lines are output open-drain pins

with 12V drive.

HDA. This is the output pin of the on-chip 14-bit

PWM D/A Converter. This line is a push-pull output

with standard drive.

ST63E69,ST63T69

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