ST6369 datasheet(47/71 Pages) STMICROELECTRONICS

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SOFTWARE DESCRIPTION

The ST6369 software has been designed to ful l y

use the hardware in the most efficient way possibl e

whil e keeping byte usage to a minimum; in short

to provide byte efficient programming capabil ity.

The ST6369 Core has the abil ity to set or cl ear

any register or RAM l ocation bit of the Data space

with a singl e instruction. Furthermore, the program

may branch to a sel ected address depending on

the status of any bit of the Data space. The carry

bit is stored with the val ue of the bit when the SET

or RES instruction is processed.

Addressing Modes

The ST6369 Core has 9 addressing modes which

are described in the fol l owing paragraphs. The

ST6369

Core uses three different address

spaces: Program space, Data space, and Stack

space. Program space contains the instructions

which are to be executed, pl us the data for imme-

diate mode instructions. Data space contains the

Accumul ator, the X,Y,V and W registers, periph-

eral andInput/Outputregisters, the RAM l ocations

and Data ROM l ocations (for storage of tabl es and

constants). Stack space contains six 12-bit RAM

cel l s used to stack the return addresses for sub-

routines and interrupts.

Immediate. In the immediate addressing mode,

the operand of the instruction fol l ows the opcode

l ocation. As the operand is a ROM byte, the imme-

diate addressing mode is used to access constants

which do not change during program execution

(e.g., a constant used to initial ize a l oop counter).

Direct. In the direct addressing mode, the address

of the byte that is processed by the instruction is

stored in the l ocation that fol l ows the opcode.

Direct addressing al l ows the user to directl y ad-

dress the 256 bytes in Data Space memory with a

singl e two-byte instruction.

Short Direct. The Core can address the four RAM

registers X,Y,V,W (l ocations 80H, 81H, 82H, 83H)

in the short-direct addressing mode. In this case,

the instruction is onl y one byte and the sel ection

of the l ocation to be processed is contained in the

opcode. Short direct addressing is a subset of the

direct addressing mode. (Note that 80H and 81H

are al so indirect registers).

Extended. In the extended addressing mode, the

12-bit address needed to define the instruction is

obtained by concatenating the four l ess significant

bits of the opcode with the byte fol l owing the

opcode. The instructions (JP, CALL) that use the

extended addressing mode are abl e to branch to

any address of the 4K bytes Program space.

An extended addressing mode instruction is two-

byte l ong.

Program Counter Relative. The rel ative address-

ing mode is onl y used in conditional branch in-

structions. The instruction is used to perform a test

and, if the condition is true, a branch with a span of

-15 to +16 l ocations around the address of the

rel ative instruction. If the condition is not true, the

instruction that fol l ows the rel ative instruction is

executed. The rel ative addressing mode instruc-

tion is one-byte l ong. The opcode is obtained in

adding the three most significant bits that charac-

terize the kind of the test, one bit that determines

whether the branch is a forward (when it is 0) or

backward (when it is 1) branch and the four l ess

significant bits that give the span of the branch (0H

to FH) that must be added or subtracted to the

address of the rel ative instruction to obtain the

address of the branch.

Bit Direct. In the bit direct addressing mode, the

bit to be set or cl eared is part of the opcode, and

the byte fol l owing the opcode points to the ad-

dress of the byte in which the specified bit must be

set or cl eared. Thus, any bit in the 256 l ocations

of Data space memory can be set or cl eared.

Bit Test & Branch. The bit test and branch ad-

dressing mode is a combination of direct address-

ing and rel ative addressing. The bit test and

branch instruction is three-byte l ong. The bit iden-

tification and the tested condition are incl uded in

the opcode byte. The address of the byte to be

tested fol l ows immediatel y the opcode in the

Program space. The third byte is the jump dis-

pl acement, which is in the range of -126 to +129.

This displ acement can be determined using a

l abel , which is converted by the assembl er.

Indirect. In the indirect addressing mode, the byte

processed by the register-indirect instruction is at

the address pointed by the content of one of the

indirect registers, X or Y (80H,81H). The indirect

Inherent. In the inherent addressing mode, al l the

information necessary to execute the instruction is

contained in the opcode. These instructions are

one byte l ong.

ST6369

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