ST6369 datasheet(32/71 Pages) STMICROELECTRONICS

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PS2

PS1

PS0

Divided By

016

132

064

128

Table 9. Prescaler Division Factors

TSCR

Imer 1&2 Status Control Registers

DAH Timer 1, DCH Timer 2,

Read/ Write

D7 D6 D5 D4 D3 D2 D1 D0

PS0 = Prescaler Mux. Select

PS1 = Prescaler Mux. Select

PS2 = Prescaler Mux. Select

PSI = Prescaler Initialize Bit

D4 = Timers Enable Bit

D5 = Timers Enable Bit

ETI = Enable Timer Inte rrupt

TMZ = Timer Zero Bit

Only Available in TSCR1

Figure 32. Timer Status Control Registers

TIMERS (Continued)

TMZ. Low-to-high transition indicates that the timer

count register has decrement to zero. This

bit

must be cleared by user software before to start

with a new count.

ETI. This bit, when set, enables the timer interrupt

(vector #3 for Timer 1, vector #1 for Timer 2) request.

If ETI=0 the timer interrupt is disabled. If ETI= 1 and

TMZ= 1 an interrupt request is generated.

D5. This is the timers enable bit D5. It must be

cleared to 0 together with a set to 1 of bit D4 to en-

able both Timer 1 and Timer 2 functions. It is not

implemented on TSCR2 register.

D4. This is the timers enable bit D4. This bit must

be set to 1 together with a clear to 0 of bit D5 to en-

able both Timer 1 and Timer 2 functions. It is not

implemented on TSCR2 register.

Timers

Disabled

Enabled

Reserved

PS1. Used to initialize the prescaler and inhibit its

counting while PSI = 0 the prescaler is set to 7FH

and the counter is inhibited. When PSI = 1 the pres-

caler is enabled to count downwards. As long as

PSI= 0 both counter and prescaler are not running.

PS2-PS0. These bits select the division ratio of the

prescaler register. (see table 9)

The TSCR1 and TSCR2 registers are cleared on

reset. The correct D4-D5 combination must be

written in TSCR1 by user’s software to enable the

operation of Timer 1 and Timer 2.

TCR

Timer Counter 1&2 Register

D3H Timer 1, DBH Timer 2, Read/ Write

D7 D6 D5 D4 D3 D2 D1 D0

D7 - D0 = Counter bits

Figure 33. Timer Counter Registers

PSC

TimerPrescaler 1&2 Register

D2H Timer 1, DAH Timer 2, Read/ Write

D7 D6 D5 D4 D3 D2 D1 D0

D6 - D0 = Prescaler bits

Always read as “0”

Figure 34. Timer Counter Registers

ST6369

28/67

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