ST6369 datasheet(18/71 Pages) STMICROELECTRONICS

18 / 71 page

Through the programming of the Data RAM Bank

bank or page leaving unaffected the way to ad-

dress the static registers. The way to address the

“dynamic” page is to set the DRBR as described in

Table 5 (e.g. to select EEPROM page 0, the DRBR

has to be loaded with content 01H, see Data

RAM/EEPROM addressing for additional informa-

tion). Bits 0, 1 and 7 of the DRBR are dedicated to

the EEPROM.

The EEPROM pages do not require dedicated in-

structions to be accessed in reading or writing. The

EEPROM is controlled by the EEPROM Control

be read just like any other data location, also in terms

of access time.

To write an EEPROM location takes an average

time of 5 ms (10ms max) and during this time the

EEPROM is not accessible by the Core. A busy

flag can be read by the Core to know the EEPROM

status before trying any access. In writing the

EEPROM can work in two modes: Byte Mode

(BMODE)

and

Parallel

Mode

(PMODE).

The BMODE is the normal way to use the

EEPROM and consists in accessing one byte at a

time. The PMODE consists in accessing 8 bytes

per time.

D7. Not used

SB. WRITE ONLY. If this bit is set the EEPROM is

disabled (any access will be meaningless) and

the

power consumption of the EEPROM is re-

duced to the leakage values.

D5, D4. Reserved for testing purposes, they must

be set to zero.

PS. SET ONLY. Once in Parallel Mode, as soon as

the user software sets the PS bit the parallel writ-

ing of the 8 adjacent registers will start. PS is inter-

nally reset at the end of the programming

procedure. Note that less than 8 bytes can be writ-

ten; after parallel programming the remaining un-

defined bytes will have no particular content.

PE. WRITE ONLY. This bit must be set by the

user program in order to perform parallel program-

ming (more bytes per time). If PE is set and the

“parallel start bit” (PS) is low, up to 8 adjacent bytes

can be written at the maximum speed, the content

being stored in volatile registers. These 8 adjacent

bytes can be considered as row, whose A7, A6,

A5, A4, A3 are fixed while A2, A1 and A0 are the

changing bytes. PE is automatically reset at the

end of any parallel programming procedure. PE

can be reset by the user software before starting

the programming procedure, leaving unchanged

the EEPROM registers.

BS. READ ONLY. This bit will be automatically set

by the CORE when the user program modifies an

EEPROM register. The user program has to test it

before any read or write EEPROM operation; any

attempt to access the EEPROM while “busy bit” is

set will be aborted and the writing procedure in pro-

gress completed.

EN. WRITE ONLY. This bit MUST be set to one in

order to write any EEPROM register. If the user

program will attempt to write the EEPROM when

EN= “0” the involved registers will be unaffected

and the ”busy bit” will not be set.

AfterRESET thecontent of EECR register will be00H.

Notes :

When the EEPROM is busy (BS=”1”) the EECR

can not be accessed in write mode, it is only possi-

ble to read BS status. This implies that as long as

the EEPROM is busy it is not possible to change

the status of the EEPROM control register. EECR

bits 4 and 5 are reserved for test purposes, and

must never be set to “1”.

Additional Notes on Parallel Mode. If the user

wants to perform a parallel programming the first

action should be the set to one the PE bit; from this

moment the first time the EEPROM will be ad-

dressed in writing, the ROW address will be

latched and it will be possible to change it only at

the end of the programming procedure or by reset-

MEMORY SPACES (Continued)

EECR

EEPROM Control Register

(EAH, Read/Wr ite)

D7 D6 D5 D4 D3 D2 D1 D0

EN = EEPROM Enable Bit

BS = EEPROM Busy Bit

PE = Parallel Mode Enable Bit

PS = Parallel Start Bit

Reserved (Must be set Low)

SB = Stand-by Enable Bit

Unused

Figure 17. EEPROM Control Register

ST6369

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