ST6369 datasheet(43/71 Pages) STMICROELECTRONICS

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14-BIT PWM D/A CONVERTER

The ST6369 PWM D/A CONVERTER (HDA) is

composed of a 14-bit counter that allows the con-

version of the digital content in an analog voltage,

available at the HDA output pin, by using Pulse

Width Modification (PWM), and Bit Rate Multiplier

(BRM) techniques.

The tuning word consists of a 14-bit word con-

tained in the registers HDADATA1 (location 0EEH)

and HDADATA2 (location 0EFH). Coarse tuning

(PWM) is performed using the seven MSBits, while

fine tuning (BRM) is performed using the data in

the seven LSBits. With all zeros loaded the output

is zero; as the tuning voltage increases from all ze-

ros, the number of pulses in one period increas to

128 with all pulses being the same width. For val-

ues larger than 128, the PWM takes over and the

number of pulses in one period remains constant

at 128, but the width changes. At the other end of

the scale, when almost all ones are loaded, the

pulses will start to link together and the number of

pulses will decrease. When all ones are loaded,

the output will be almost 100% high but will have a

low pulse (1/16384 of the high pulse).

Output Details

Inside the on-chip D/A CONVERTER are included

the register latches, a reference counter, PWM and

BRM control circuitry. In the ST6369 the clock for

the 14-bit reference counter is 2MHz derived from

the 8MHz system clock. From the circuit point of

view, the seven most significant bits control the

coarse tuning, while the seven least significant bits

control the fine tuning. From the application and

software point of view, the 14 bits can be consid-

ered as one binary number.

As already mentioned the coarse tuning consists of

a PWM signal with 128 steps ; we can consider the

fine tuning to cover 128 coarse tuning cycles. The

addition of pulses is described in the following Ta-

ble.

FIne Tuning

(7 LSB)

° of Pulses added at

the following cycles

(0...127)

0000001

0000010

32, 96

0000100

16, 48, 80, 112

0001000

8, 24, ....104, 120

0010000

4, 12, ....116, 124

0100000

2, 6, .....122, 126

1000000

1, 3, .....125, 127

Table 11. Fine Tuning Pulse Addition

The HDA output pin has a standard drivepush-pull

output configuration.

HDA Tuning Cell Registers

D7-D0. These are the 8 least significant HDA data

bits. Bit 0 is the LSB. This register is undefined on

reset.

D7-D6. These bits are not used.

D5-D0. These are the 6 most significant HDA data

bits. Bit 5 is the MSB. This register is undefined on

reset.

HDADR1

HDA Data Register 1

(0EEH, Write only)

D7 D6 D5 D4 D3 D2 D1 D0

HDA Data Bits (LSB)

Figure 48. HDA Data Register 1

HDADR2

HDA Data Register 2

(0EFH, Write only)

D7 D6 D5 D4 D3 D2 D1 D0

HDA Data Bits (LSB)

Unuse d

Figure 49. HDA Data Register 2

ST6369

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