ST6369 datasheet(60/71 Pages) STMICROELECTRONICS

60 / 71 page

VDD

PC0 ( SCL )

PC1 ( SDA )

PC2

PC3 ( SEN )

PC4 ( PWRIN )

PC5

PC6 ( HSYNC )

PC7

RESET

OSCOUT

OSCIN

HDA

TEST / V

VSYNC

N.C.

DA1

DA0

DA2

DA3

DA4

DA5

PB1

PB2

PB4

PB5

PB6

PA0

PA1

PA2

PA3

PA4

PA5

PA6 ( HD0 )

PA7 ( HD1 )

VR0F1375

ST63E69

ST63T69

Figure 1. ST63E69, T69 Pin Configuration

GENERAL DESCRIPTION

The ST63E69 microcontroller is member of the 8-bit

HCMOS ST638x family, a series of devices specially

oriented to Digital Controlled Multi Frequency Moni-

tor applications. They are the EPROM/OTP versions

of the ST6369 ROM device and are suitable for prod-

uct prototyping and low volume production. ST6369

is based on a building block approach: a common

core is surrounded by a combination of on-chip pe-

ripherals (macrocells) available from a standard li-

brary. Theseperipherals are designed with the same

Core technology providing full compatibility and

short design time. Many of these macrocells are spe-

cially dedicated to DCMF monitor applications. The

macrocells of the ST6369 are: two Timer peripher-

als each including an 8-bit counter with a 7-bit soft-

ware programmable prescaler (Timer), a digital

hardware activated watchdog function (DHWD), a

14-bit voltage synthesis tuning peripheral, a Serial

Peripheral Interface (SPI), six 6-bit PWM D/A con-

verters, an A/D converter with 0.5V resolution, a 14-

bit PWM D/A converter. In addition the following

memory resources are available: program EPROM

(8K), data RAM (256 bytes), EEPROM (384 bytes).

ST63E69,ST63T69

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