ST6369 datasheet(27/71 Pages) STMICROELECTRONICS

27 / 71 page

INPUT/OUTPUT PORTS

The ST6369 microcontrollers use three standard

I/O ports (A,B,C) with up to eight pins on each port;

refer to the device pin configurations to see which

pins are available.

Each line can be individually programmed either in

the input mode or the output mode as follows by

software.

Output

Input with on-chip pull-up resistor (selected by

software)

Input without on-chip pull-up resistor (selected

by software)

Note: pins with 12V open-drain capability do not

have pull-up resistors.

In output mode the following hardware configura-

tions are available:

Open-drain output 12V (PA4-PA7, PC4-PC7)

Open-drain output 5V (PC0-PC3)

Push-pull output (PA0-PA3, PB0-PB6)

The lines are organized in three ports (port A,B,C).

The ports occupy 6 registers in the data space.

Each bit of these registers is associated with a par-

ticular line (for instance, the bits 0 of the Port A

Data and Direction registers are associated with

the PA0 line of Port A).

There are three Data registers (DRA, DRB, DRC),

that are used to read the voltage level values of the

lines programmed in the input mode, or to write the

logic value of the signal to be output on the lines

configured in the output mode. The port Data Reg-

isters can be read to get the effective logic levels of

the pins, but they can be also written by the user

software, in conjunction with the related Data Di-

rection Register, to select the different input mode

options. Single-bit operations on I/O registers (bit

set/reset instructions) are possible but care is nec-

essary because reading in input mode is made

from I/O pins and therefore might be influenced by

the external load, while writing will directly affect

the Port data register causing an undesired

changes of the input configuration. The three Data

Direction registers (DDRA, DDRB, DDRC) allow

the selection of the direction of each pin (input or

output).

All the I/O registers can be read or written as any

other RAM location of the data space, so no extra

RAM cell is needed for port data storing and ma-

nipulation. During the initialization of the MCU, all

the I/O registers are cleared and the input mode

with pull-up is selected on all the pins thusavoiding

pin conflicts (with the exception of PC2 that is set in

output mode and is set high ie. high impedance).

Details of I/O Ports

When programmed as an input a pull-up resistor (if

available) can be switched active under program

control. When programmed as an output the I/O

port will operate either in the push-pull mode or the

open-drain mode according to the hardware fixed

configuration as specified below.

Port A. PA0-PA3 are available as push-pull when

outputs. PA4-PA7 are available as open-drain (no

push-pull programmability) capable of withstand-

ing 12V (no resistive pull-up in input mode). PA6-

PA7 has been specially designed for higher driving

capability and are able to sink 25mA with a maxi-

mum VOL of 1V.

Port B. All lines are configured as push-pull when

outputs.

Port C. PC0-PC3 are available as open-drain ca-

pable of withstanding a maximum VDD+0.3V. PC4-

PC7 are available as open-drain capable of

withstanding 12V (no resistive pull-up in input

mode). Some lines are also used as I/O buffers for

signals coming from the on-chip SPI.

In this case the final signal on the output pin is

equivalent to a wired AND with the programmed

data output.

If the user needs to use the serial peripheral, the

I/O line should be set in output mode while the

open-drain configuration is hardware fixed; the

corresponding data bit must set to one. If the

latchedinterrupt functionsare used (HSYNC, PWRIN)

then the corresponding pins should be set to input

mode.

On ST6369 the I/O pins with double or special

functions are:

PC0/SCL (connected to the SPI clock signal)

PC1/SDA (connected to the SPI data signal)

PC3/SEN (connected to the SPI enable signal)

PC4/PWRIN (connected to the PWRIN inter-

rupt latch)

PC6/HSYNC (connected to the HSYNC inter-

rupt latch)

All the Port A,B and C I/O lines have Schmitt-trigger

input configuration with a typical hysteresis of 1V.

ST6369

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