ST7263 datasheet(75/109 Pages) STMICROELECTRONICS

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ST7263

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I²C BUS INTERFACE (Cont’d)

5.7.4 Functional Description

Refer to the CR, SR1 and SR2 registers in Section

0.1.7. for the bit definitions.

By default the I²C interface operates in Slave

mode (M/SL bit is cleared) except when it initiates

a transmit or receive sequence.

5.7.4.1 Slave Mode

As soon as a start condition is detected, the

address is received from the SDA line and sent to

the shift register; then it is compared with the

address of the interface or the General Call

address (if selected by software).

Address not matched: the interface ignores it

and waits for another Start condition.

Address matched: the interface generates in se-

quence:

– An Acknowledge pulse is generated if the ACK

bit is set.

– EVF and ADSL bits are set with an interrupt if the

ITE bit is set.

Then the interface waits for a read of the SR1 reg-

ister, holding the SCL line low (see Figure 3

Transfer sequencing EV1).

Next, software must read the DR register to deter-

mine from the least significant bit if the slave must

enter Receiver or Transmitter mode.

Slave Receiver

Following the address reception and after SR1

from the SDA line into the DR register via the inter-

nal shift register. After each byte the interface gen-

erates in sequence:

– An Acknowledge pulse is generated if the ACK

bit is set

– EVF and BTF bits are set with an interrupt if the

ITE bit is set.

Then the interface waits for a read of the SR1 reg-

ister followed by a read of the DR register, holding

the SCL line low (see Figure 3 Transfer sequenc-

ing EV2).

Slave Transmitter

Following the address reception and after the SR1

the DR register to the SDA line via the internal shift

The slave waits for a read of the SR1 register fol-

lowed by a write in the DR register, holding the

SCL line low (see Figure 3 Transfer sequencing

EV3).

When the acknowledge pulse is received:

– The EVF and BTF bits are set by hardware with

an interrupt if the ITE bit is set.

Closing Slave Communication

After the last data byte is transferred a Stop Con-

dition is generated by the master. The interface

detects this condition and sets:

– EVF and STOPF bits with an interrupt if the ITE

bit is set.

Then the interface waits for a read of the SR2 reg-

ister (see Figure 3 Transfer sequencing EV4).

Error Cases

– BERR: Detection of a Stop or a Start condition

during a byte transfer. In this case, the EVF and

BERR bits are set with an interrupt if the ITE bit

is set.

If it is a Stop condition, then the interface dis-

cards the data, released the lines and waits for

another Start condition.

If it is a Start condition, then the interface dis-

cards the data and waits for the next slave ad-

dress on the bus.

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set with an inter-

rupt if the ITE bit is set.

Note: In both cases, the SCL line is not held low;

however, the SDA line can remain low due to pos-

sible “0” bits transmitted last. It is then necessary

to release both lines by software.

How to Release the SDA / SCL lines

Set and subsequently clear the STOP bit while

BTF is set. The SDA/SCL lines are released after

the transfer of the current byte.

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