ST7263 datasheet(34/109 Pages) STMICROELECTRONICS

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ST7263

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WATCHDOG TIMER (Cont’d)

5.3.3 Functional Description

The counter value stored in the CR register (bits

T6:T0), is decremented every 49,152 machine cy-

cles, and the length of the timeout period can be

programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T6:T0) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates

a reset cycle pulling low the reset pin for typically

500ns.

The application program must write in the CR reg-

ister at regular intervals during normal operation to

prevent an MCU reset. The value to be stored in

the CR register must be between FFh and C0h

(see Table 14 . Watchdog Timing (fCPU = 8

MHz)):

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to prevent generating an imme-

diate reset

– The T5:T0 bits contain the number of increments

which represents the time delay before the

watchdog produces a reset.

Table 14. Watchdog Timing (fCPU = 8 MHz)

Notes: Following a reset, the watchdog is disa-

bled. Once activated it cannot be disabled, except

by a reset.

The T6 bit can be used to generate a software re-

set (the WDGA bit is set and the T6 bit is cleared).

5.3.3.1 Using Halt Mode with the WDG

The HALT instruction stops the oscillator. When

the oscillator is stopped, the WDG stops counting

and is no longer able to generate a reset until the

microcontroller receives an external interrupt or a

reset.

If an external interrupt is received, the WDG re-

starts counting after 4096 CPU clocks. If a reset is

generated, the WDG is disabled (reset state).

Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG

reset immediately after waking up the microcon-

troller.

– When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O

as “Input Pull-up with Interrupt” before executing

the HALT instruction. The main reason for this is

that the I/O may be wrongly configured due to ex-

ternal interference or by an unforeseen logical

condition.

– For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precau-

tionary measure.

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a

program counter failure, it is advised to clear all

occurrences of the data value 0x8E from memo-

ry. For example, avoid defining a constant in

ROM with the value 0x8E.

– As the HALT instruction clears the I bit in the CC

to clear all pending interrupt bits before execut-

ing the HALT instruction. This avoids entering

other peripheral interrupt routines after executing

the external interrupt routine corresponding to

the wake-up event (reset or external interrupt).

5.3.4 Interrupts

None.

5.3.5 Register Description

CONTROL REGISTER (CR)

Read /Write

Reset Value: 0111 1111 (7F h)

Bit 7 = WDGA

Activation bit.

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Bit 6:0 = T[6:0]

7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset

is produced when it rolls over from 40h to 3Fh (T6

becomes cleared).

CR Register

initial value

WDG timeout period

(ms)

Max

FFh

393.216

Min

C0h

6.144

WDGA

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