ST7263 datasheet(78/109 Pages) STMICROELECTRONICS

部件名	ST7263

功能描述	LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C

PDF	109 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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ST7263

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I²C BUS INTERFACE (Cont’d)

5.7.5 Low Power Modes

5.7.6 Interrupts

Figure 41. Event Flags and Interrupt Generation

The I²C interrupt events are connected to the

same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the I-bit in the CC

Mode

Description

WAIT

No effect on I²C interface.

I²C interrupts exit from Wait mode.

HALT

I²C registers are frozen.

In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The I²C

interface resumes operation when the MCU is woken up by an interrupt with “exit from Halt

mode” capability.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

End of Byte Transfer Event

BTF

ITE

Yes

Address Matched Event (Slave mode)

ADSEL

Yes

Start Bit Generation Event (Master mode)

Yes

Acknowledge Failure Event

Yes

Stop Detection Event (Slave mode)

STOPF

Yes

Arbitration Lost Event (Multimaster configuration)

ARLO

Yes

Bus Error Event

BERR

Yes

BTF

ADSL

STOPF

ARLO

BERR

EVF

INTERRUPT

ITE

* EVF can also be set by EV6 or an error from the SR2 register.

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