ST7263 datasheet(76/109 Pages) STMICROELECTRONICS

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ST7263

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I²C BUS INTERFACE (Cont’d)

5.7.4.2 Master Mode

To switch from default Slave mode to Master

mode, a Start condition generation is needed.

Start Condition and Transmit Slave Address

Setting the START bit while the BUSY bit is

cleared causes the interface to switch to Master

mode (M/SL bit set) and generates a Start condi-

tion.

Once the Start condition is sent:

– The EVF and SB bits are set by hardware with

an interrupt if the ITE bit is set.

Then the master waits for a read of the SR1 regis-

ter followed by a write in the DR register with the

Slave address byte, holding the SCL line low

(see Figure 3 Transfer sequencing EV5).

Then the slave address byte is sent to the SDA

line via the internal shift register.

After completion of this transfer (and acknowledge

from the slave if the ACK bit is set):

– The EVF bit is set by hardware with interrupt

generation if the ITE bit is set.

Then the master waits for a read of the SR1 regis-

ter followed by a write in the CR register (for exam-

ple set PE bit), holding the SCL line low (see Fig-

ure 3 Transfer sequencing EV6).

Next the master must enter Receiver or Transmit-

ter mode.

Master Receiver

Following the address transmission and after the

SR1 and CR registers have been accessed, the

master receives bytes from the SDA line into the

DR register via the internal shift register. After

each byte the interface generates in sequence:

– An Acknowledge pulse is generated if if the ACK

bit is set

– EVF and BTF bits are set by hardware with an in-

terrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 reg-

ister followed by a read of the DR register, holding

the SCL line low (see Figure 3 Transfer sequenc-

ing EV7).

To close the communication: before reading the

last byte from the DR register, set the STOP bit to

generate the Stop condition. The interface returns

automatically to slave mode (M/SL bit cleared).

Note: In order to generate the non-acknowledge

pulse after the last received data byte, the ACK bit

must be cleared just before reading the second

last data byte.

Master Transmitter

Following the address transmission and after SR1

from the DR register to the SDA line via the inter-

nal shift register.

The master waits for a read of the SR1 register fol-

lowed by a write in the DR register, holding the

SCL line low (see Figure 3 Transfer sequencing

EV8).

When the acknowledge bit is received, the

interface sets:

– EVF and BTF bits with an interrupt if the ITE bit

is set.

To close the communication: after writing the last

byte to the DR register, set the STOP bit to gener-

ate the Stop condition. The interface goes auto-

matically back to slave mode (M/SL bit cleared).

Error Cases

– BERR: Detection of a Stop or a Start condition

during a byte transfer. In this case, the EVF and

BERR bits are set by hardware with an interrupt

if the ITE bit is set.

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set by hardware

with an interrupt if the ITE bit is set. To resume,

set the START or STOP bit.

– ARLO: Detection of an arbitration lost condition.

In this case the ARLO bit is set by hardware (with

an interrupt if the ITE bit is set and the interface

goes automatically back to slave mode (the M/SL

bit is cleared).

Note: In all these cases, the SCL line is not held

low; however, the SDA line can remain low due to

possible “0” bits transmitted last. It is then neces-

sary to release both lines by software.

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